DP8421AV-25 National Semiconductor, DP8421AV-25 Datasheet - Page 37

• Manufacturer Part Number: DP8421AV-25
• Description: IC CTRLR/DVR CMOS PROGRAM 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8421AV-25

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8421AV-25

10 0 Dual Accessing (DP8422A)
The DP8422A has all the functions previously described In
addition to those features the DP8422A also has the capa-
bilities to arbitrate among refresh Port A and a second port
Port B This allows two CPUs to access a common DRAM
array DRAM refresh has the highest priority followed by the
currently granted port The ungranted port has the lowest
priority The last granted port will continue to stay granted
even after the access has terminated until an access re-
quest is received from the ungranted port (see Figure 32a )
The dual access configuration assumes that both Port A
and Port B are synchronous to the system clock If they are
not synchronous to the system clock they should be exter-
nally synchronized (Ex By running the access requests
through several Flip-Flops see Figure 34a )
10 1 PORT B ACCESS MODE
Port B accesses are initiated from a single input AREQB
When AREQB is asserted an access request is generated
If GRANTB is asserted and a refresh is not taking place or
precharge time is not required RAS will be asserted when
AREQB is asserted Once AREQB is asserted it must stay
asserted until the access is over AREQB negated negates
RAS as shown in Figure 32b Note that if ECAS0
programming the CAS outputs may be held asserted (be-
yond RASn negating) by continuing to assert the appropri-
ate ECASn inputs (the same as Port A accesses) If Port B
is not granted the access will begin on the first or second
positive edge of CLK after GRANTB is asserted (See R0
R1 programming bit definitions) as shown in Figure 32c as-
suming that Port A is not accessing the DRAM (CS ADS
ALE and AREQ) and RAS precharge for the particular bank
FIGURE 32b Access Request for Port B
FIGURE 32c Delayed Port B Access
e
1 during
37
has completed It is important to note that for GRANTB to
transition to Port B Port A must not be requesting an ac-
cess at a rising clock edge (or locked) and Port B must be
requesting an access at that rising clock edge Port A can
request an access through CS and ADS ALE or CS and
AREQ Therefore during an interleaved access where CS
and ADS ALE become asserted before AREQ from the pre-
vious access is negated Port A will retain GRANTB
whether AREQB is asserted or not
Since there is no chip select for Port B AREQB must incor-
porate this signal This mode of accessing is similar to Mode
1 accessing for Port A
Explanation of Terms
AREQA
AREQB
LOCK
FIGURE 32a DP8422A Port A Port B Arbitration
State Diagram This arbitration may take place
e
e
e
that is currently GRANTed
during the ‘‘ACCESS’’ or ‘‘REFRESH’’
Chip Selected access request from Port A
Chip Selected access request from Port B
Externally controlled LOCKing of the Port
state (see Figure 13a )
TL F 8588 – F9
TL F 8588 – E4
TL F 8588 – E5
e
0