ISL6296ADRTZ-T Intersil, ISL6296ADRTZ-T Datasheet
ISL6296ADRTZ-T
Specifications of ISL6296ADRTZ-T
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ISL6296ADRTZ-T Summary of contents
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... XSD NC NC TIO CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 FlexiHash is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. ISL6296A FN6567.3 AN1165 “ISL6296 Evaluation Kit” AN1167 “Implementing XSD Host Using TB363 “ ...
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... Ordering Information PART NUMBER (Note) ISL6296ADHZ-T* 296A ISL6296ADRTZ-T* 96A ISL6296EVAL1 ISL6296 Evaluation Kit *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). ...
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... Thermal Resistance (Typical) + 0.5V SOT-23 Package (Note 2x3 TDFN Package (Notes Maximum Junction Temperature (Plastic Package +125°C Maximum Storage Temperature Range . . . . . . . . . .-40°C to +125°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = -25°C to +85° SYMBOL TEST CONDITIONS V During normal operation DD ...
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... XSD BUS TIMING CHARACTERISTICS (Refer to XSD Bus Symbol Timing Definitions Tables on page 13) Programming Bit Rate XSD Input Deglitch Time Device Wake-Up Time Device Sleep Wait Time Auto-Sleep Time-Out Period OTP ROM Write Time Hash Calculation Time Soft-Reset Time Pin Descriptions ISL6296ADHZ-T ISL6296ADRTZ SOT-23 TDFN ...
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Typical Applications PACK+ XSD PACK- FIGURE 1. TYPICAL APPLICATION WITH THE ISL6296A POWERED BY THE BATTERY PACK+ XSD PACK- FIGURE 2. TYPICAL APPLICATION WITH THE ISL6296A POWERED BY THE XSD BUS Block Diagram XSD 5 ISL6296A ...
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Theory of Operation The ISL6296A contains all circuitry required to support battery pack authentication based on a challenge-response scheme. It provides a 16-Byte One-Time Programmable Read-Only Memory (OTPROM) space for the storage bits of secret for ...
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Auto-Sleep mode can be disabled by clearing the ASLP bit in the MSCR register. By default, Auto-Sleep is always enabled at power-up and after a soft reset. Auto-sleep function can be permanently disabled by clearing the 0-00[2] bit (the ASLP ...
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If the codes do not match up, the device is a fake device and the host may shut itself down. The flow chart in Figure ...
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XI BN 8-BIT CRC CALCULATOR CN DN POLYNOM = MA[7: 8-BIT CRC CALCULATOR CN DN POLYNOM = MB[7: 8-BIT CRC CALCULATOR XI DN POLYNOM = MC[7:6] AN ...
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... XSD Host Bus Interface Communication with the host is achieved through XSD, a light-weight subset of Intersil’s ISD single-wire bus interface. XSD is a programmable-rate, pseudo-synchronous, bidirectional, host-initiated, instruction-based, serial communication interface that allows up to two slave devices to be attached and addressed separately. It includes features to enable quick and reliable communication ...
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HOST OPEN-DRAIN Open-Drain PORT-PIN Port Pin TX RX FIGURE 8. THE CIRCUIT MODEL FOR THE XSD SERIAL BUS XSD TABLE 2. HOST TIMING DEFINITIONS OF SYMBOLS AND BUS SIGNALING PARAMETER SYM Bit Time 0. ...
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BYTES BYTES BYTES FIGURE 10. THE 16-BIT INSTRUCTION FRAME FIELD DEFINITION OPCODE DESCRIPTION 00 Write Operation 01 Read Operation (normal) 10 Read Operation (with CRC) Read from device register. Append 1-Byte CRC to the end of the ...
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Bus Transaction Protocol The XSD bus for the ISL6296A defines three types of bus transactions. Figure 11 shows the bus transaction protocol. The blue color represents the signal sent by the host and the green color stands for the signal ...
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... These registers are used during the battery pack authentication process. Table 10 describes the mapping of the Authentication registers. Bank 3 is reserved for Intersil production testing only, and will not be accessible during normal operation. Accessing the Test and Trim Registers when not in test mode will result in a bus error ...
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TABLE 9. CONTROL AND STATUS REGISTERS (BANK 1) ADDRESS NAME DESCRIPTION 1-00 MSCR Master Control 1-01 STAT Device Status ADDRESS NAME DESCRIPTION 2-00 SESL Secrets Selection 2-01 CHLG Challenge Code Register 2-05 AUTH Authentication Code Register TABLE 11. DEFAULT CONFIGURATION ...
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ADDRESS 0-06/07/08/09: AUTHENTICATION SECRET SET #2 (SE2A/B/C/D) These address locations store the second set of secrets to be used for hash calculation. Reading and writing to this register can be disabled by setting the SLO[1] bit at OTP ROM location ...
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... One way is to use a spare UART (Universal Asynchronous Receiver/Transmitter). A GPIO (General Purpose Input/Output) can be used if no UART is available for the XSD communication. Refer to Application Note AN1167 available from Intersil for more information regarding how to implement the XSD bus within a microprocessor. Pull-Up Resistor Selection ...
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VDD HOST HOST PROCESSOR LOGIC XSD Pin Series Resistor Selection A series resistor may be used to improve ESD performance of the XSD input. In Figure 13, resistor R1 and zener diode D1 provide ESD protection for the ISL6296A XSD ...
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Package Outline Drawing L8.2x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE WITH E-PAD Rev 1, 06/09 2.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW PACKAGE OUTLINE 1.65 2.00 TYPICAL RECOMMENDED LAND PATTERN 19 ISL6296A 6 PIN #1 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...