PCA8534AH/Q900/1,5 NXP Semiconductors, PCA8534AH/Q900/1,5 Datasheet - Page 20

• Manufacturer Part Number: PCA8534AH/Q900/1,5
• Description: IC LCD DRIVER 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCA8534AH/Q900/1,5

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 80µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 60
• Maximum Clock Frequency: 3046 Hz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 95 C
• Attached Touch Screen: No
• Maximum Supply Current: 20 uA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5110-2

NXP Semiconductors
PCA8534A_2
Product data sheet
7.16.2 START and STOP conditions
7.16.3 System configuration
7.16.4 Acknowledge
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves (see
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
Fig 12. Definition of START and STOP conditions
Fig 13. System configuration
•
•
•
A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
SCL
SDA
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
START condition
All information provided in this document is subject to legal disclaimers.
Figure
S
Rev. 02 — 1 June 2010
12).
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
Universal LCD driver for low multiplex rates
SLAVE
Figure
13).
TRANSMITTER
MASTER
STOP condition
PCA8534A
P
TRANSMITTER/
© NXP B.V. 2010. All rights reserved.
RECEIVER
MASTER
mbc622
mga807
SDA
SCL
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