PCF85134HL/1,118 NXP Semiconductors, PCF85134HL/1,118 Datasheet - Page 21

• Manufacturer Part Number: PCF85134HL/1,118
• Description: IC LCD DISPLAY DRVR 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF85134HL/1,118

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Digits Or Characters: Any Digit Type
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5060-2

NXP Semiconductors
PCF85134_1
Product data sheet
8.1.3 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
Acknowledgement on the I
Fig 13. System configuration
Fig 14. Acknowledgement of the I
•
•
•
•
A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
SCL
SDA
by transmitter
data output
by receiver
data output
TRANSMITTER/
SCL from
RECEIVER
master
MASTER
condition
START
Rev. 01 — 17 December 2009
S
2
RECEIVER
C-bus is illustrated in
SLAVE
2
1
C-bus
TRANSMITTER/
RECEIVER
Universal LCD driver for low multiplex rates
SLAVE
2
Figure
TRANSMITTER
14.
MASTER
not acknowledge
acknowledge
8
PCF85134
acknowledgement
clock pulse for
TRANSMITTER/
© NXP B.V. 2009. All rights reserved.
RECEIVER
MASTER
9
mbc602
mga807
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