DS1862B+ Maxim Integrated Products, DS1862B+ Datasheet - Page 23

• Manufacturer Part Number: DS1862B+
• Description: IC LASR CTRLR 7CHAN 5.5V 25CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Laser Diode Controller (Fiber Optic)r

Specifications of DS1862B+

• Data Rate: 10Gbps
• Number Of Channels: 7
• Voltage - Supply: 2.9 V ~ 5.5 V
• Current - Supply: 3mA
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 25-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The polarity of the FETG pin can also be reversed by
setting the FETG_POL bit. Once a safety fault has
occurred, the FETG pin and all of the attendant flags can
only be reset by pulsing the P-DOWN/RST pin high for the
reset time, t
bit in Byte 6Eh, bit 3. See the Power-Down/Reset Pin sec-
tion for more details.
The P-DOWN/RST pin is a multifunction input pin that
resets and/or powers down the DS1862. Since the pin is
internally pulled up, its normal state is released, which
corresponds to power-down mode. If the P-DOWN/RST
pin is released, or driven high, the DS1862 responds by
shutting down the MODSET and BIASSET currents.
Once the pin is pulled low, operation continues (if not
inhibited by a safety fault). Besides powering down the
DS1862, a high-going pulse with minimum reset time,
t
necessary to restart the DS1862, especially if it is in a
safety shutdown condition and needs to be restarted
Figure 12. Safety Fault and Shutdown Logic
RESET
(BIASSET CURRENT)
(TX-P CURRENT)
(TX-P CURRENT)
, can be applied to the P-DOWN/RST pin. This is
BIASSET (PIN)
XFP Laser Control and Digital Diagnostic IC
BMD (PIN)
BMD (PIN)
SOFT P-DOWN/RST
P-DOWN/RST (PIN)
RESET
SAFETY FLAG
SOFT TX-D
TX-D (PIN)
, or by toggling the SOFT P-DOWN/RST
THRESHOLD
THRESHOLD
THRESHOLD
ADC
ADC
ADC
Power-Down/Reset Pin
SHUTDOWN
____________________________________________________________________
FLAG
HIGH TX-P MASK
HIGH BIAS MASK
LOW TX-P MASK
SHUTDOWN LOGIC
QT HIGH TX-P FLAG
QT HIGH BIAS FLAG
QT LOW TX-P FLAG
after the safety condition has been rectified. See the
timing diagrams for proper pin timing.
During power-down mode I
below 10μA, effectively shutting down the laser. FETG
is not asserted and safety faults do not occur during
this period. During power-down, I
still active, but the signal conditioner pins EN1 and EN2
are noncontrollable and automatically change to the
states: EN1 = 1 and EN2 = 0. Other internal flags/sig-
nals that are based on the signal conditioner inputs still
reflect the status on the signal conditioner pins during
power-down. For example, RX-LOS still reflects the sta-
tus of SC-RX-LOS, and MOD-NR still reflects the logical
states for the signal conditioner pins. Similarly, it is possi-
ble for FETG to be asserted, even though the BIASSET
and MODSET currents are shut down. However, during
power-down and a short period, t
up, TX-P Low flag is ignored (internally automatically
masked out) and does not contribute to FETG’s logic.
QT LOW
TX-P FLAG
QT HIGH
TX-P FLAG
QT HIGH
BIAS FLAG
0
1
FETG_POL
Power-Down Functionality
DRIVE A P-CHANNEL SWITCH
DRIVE A N-CHANNEL SWITCH
BIASSET
LATCHED-TX-FAULT
FETG_POL
PDR-OFF
SAFETY FLAG
2
C communication is
and I
, during power-
MODSET
FETG (PIN)
drop
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