LM87CIMT/NOPB National Semiconductor, LM87CIMT/NOPB Datasheet - Page 22

• Manufacturer Part Number: LM87CIMT/NOPB
• Description: IC INTERFACE SER MONITOR 24TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM87CIMT/NOPB

• Function: Hardware Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Speed Control, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: I²C™/SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 2.8 V ~ 3.8 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM87CIMT; *LM87CIMT/NOPB; LM87CIMT

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10.0 RESET# I/O
RESET# is intended to provide a master reset to devices
connected to this line. Setting Bit 4 in Configuration Register
1 high outputs a 20 ms (minimum) low pulse on this line, at
the end of which Bit 4 in the Configuration Register automat-
ically clears. Again, the label for this pin is only its suggested
use. In applications where the RESET# capability is not need-
ed it can be used for any type of digital control that requires
a 20 ms (mimimum) active low, open-drain output.
RESET# operates as an input when not activated by Config-
uration Register 1. Setting this line low will reset all of the
registers in the LM87 to their power on default state. All Value
RAM locations will not be affected except for the DAC Data
Register.
11.0 NAND TREE TESTS
A NAND tree is provided in the LM87 for Automated Test
Equipment (ATE) board level connectivity testing. DACOut/
FIGURE 11. LM87 Interrupt Structure
22
NTEST_IN, INT#, THERM#, V
from NAND tree testing. Taking DACOut/NTEST_IN high dur-
ing power up activates the NAND Tree test mode. After the
first SMBus access to the LM87 the NAND Tree test mode is
terminated and cannot be reactivated without repeating the
power up sequence. To perform a NAND tree test, all pins
included in the NAND tree should be driven to 1 forcing the
ADD/NTEST_OUT high. Each individual pin starting with
SMBData and concluding with RESET# (excluding DACOut/
NTEST_IN, INT#, THERM#, V
with the resulting toggle observed on the ADD/NTEST_OUT
pin. Allow for a typical propagation delay of 500 ns.
+
+
and GND pins are excluded
and GND) can be taken low
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