LM87CIMT/NOPB National Semiconductor, LM87CIMT/NOPB Datasheet - Page 27

• Manufacturer Part Number: LM87CIMT/NOPB
• Description: IC INTERFACE SER MONITOR 24TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM87CIMT/NOPB

• Function: Hardware Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Speed Control, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: I²C™/SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 2.8 V ~ 3.8 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM87CIMT; *LM87CIMT/NOPB; LM87CIMT

0-6 Reserved
Bit
Bit
Bit
Bit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
7
13.7 Interrupt Status Register 2—Address 42h
Power on default – <7:0> = 0000 0000 binary
13.8 Interrupt Mask Register 1—Address 43h
Power on default – <7:0> = 0000 0000 binary
13.9 Interrupt Mask Register 2—Address 44h
Power on default – <7:0> = 0000 0000 binary
13.10 Reserved Register —Address 45h
Power on default – <7:0> = 00h. Read/Write for backwards
compatibility.
+12Vin
Vccp2
Reserved
Reserved
CI
THERM#
D1 Fault
D2 Fault
+2.5Vin/D2+ Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Vccp1
Vcc
+5Vin
Int. Temp.
Ext. Temp.
FAN1/AIN1
FAN2/AIN2
+12Vin
Vccp2
Reserved
Reserved
Chassis Intrusion
THERM#
D1 Fault
D2 Fault
CI Clear
Name
Name
Name
Name
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write
Read/Write
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT# interrupt.
Read/Write
Read/Write A one outputs a minimum 20 ms (minimum) active low pulse on the Chassis Intrusion pin. The
Read/Write
Read/Write
Read/Write
register bit self clears after the pulse has been output.
A one indicates a High or Low limit has been exceeded.
A one indicates a High or Low limit has been exceeded.
A one indicates the CI (Chassis Intrusion) input has gone high.
A one indicates the THERM# input has been pulled low by external circuitry.
A one indicates the D1 inputs are shorted to Vcc or open circuit.
A one indicates the D2 inputs are shorted to Vcc or open circuit.
27
13.11 CI Clear Register—Address 46h
Power on default – <7:0> = 0000 0000 binary
Description
Description
Description
Description
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