LTC1873EG#TR Linear Technology, LTC1873EG#TR Datasheet - Page 14

• Manufacturer Part Number: LTC1873EG#TR
• Description: IC REG SW 2PH DUAL SYNC 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC1873EG#TR

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 750kHz
• Duty Cycle: 93%
• Voltage - Supply: 3 V ~ 7 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Frequency-max: 750kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC1873
is most severe, and by including a few millivolts offset in
the comparator that monitors the SW node. Despite these
precautions, some combinations of inductor and layout
parasitics can cause the LTC1873 to enter discontinuous
mode erratically. In many cases, the time that QB turns off
will correspond to a peak in the ringing waveform at the
SW pin (Figure 6). This erratic operation isn’t pretty, but
retains much of the efficiency benefit of discontinuous
mode and maintains regulation at all times.
14
Figure 6. Ringing at SW Causes Discontinuous
Comparator to Trip Early
V
SW
I
RIPPLE
Figure 5b. Discontinuous Mode
0V
5V
0V
Figure 5a. Continuous Mode
U
I
RIPPLE
BLANK
TIME
50ns
DISCONTINUOUS
TURNS OFF BG
COMPARATOR
U
TIME
TIME
TIME
W
TIME
I
1873 F06
AVERAGE
I
AVERAGE
1873 F05b
1873 F05a
U
Burst Mode Operation
Discontinuous mode removes a loss term due to resistive
drop in QB, but the LTC1873 is still switching QT and QB
on and off once a cycle. Each time an external MOSFET is
turned on, the internal driver must charge its gate to V
Each time it is turned off, that charge is lost to ground. At
the high switching frequencies that the LTC1873 operates
at, the charge lost to the gates can add up to tens of
milliamps from V
this quickly become the dominant power loss term, reduc-
ing efficiency once again.
Once again, the LTC1873 switches to a new mode to
minimize efficiency loss: Burst Mode operation. As the
circuit goes deeper and deeper into discontinuous mode,
the total time QT and QB are on reduces. However, the ratio
of the time that QT is on to the time that QB is on must
remain constant for the output to stay in regulation. An
internal timer circuit forces QT to stay on for at least 10%
of a normal switching cycle. When the load drops to the
point that the output requires less than 10% on-time at QT,
the output voltage will begin to rise. The LTC1873 senses
this rise and shuts both QT and QB off completely, skip-
ping several switching cycles until the output falls back
into range. It then resumes switching in discontinuous
mode with QT at 10% duty cycle and the burst sequence
repeats. The total deviation from the regulated output is
within the 1.5% regulation tolerance of the LTC1873.
In Burst Mode operation, both resistive loss and switching
loss are minimized while keeping the output in regulation.
The ripple current will be set by the 10% QT on-time and
the input supply voltage and is the lowest of all three
operating modes. As the load current falls to zero in Burst
Mode operation, the most significant loss term becomes
the 3mA quiescent current drawn by each side of the
LTC1873—usually much less than the minimum load
current in a typical low voltage logic system. Burst Mode
operation maximizes efficiency at low load currents, but
can cause low frequency ripple in the output voltage as the
cycle-skipping circuitry switches on and off.
CC
. As the load current continues to drop,
CC
.