LTC1873EG#TR Linear Technology, LTC1873EG#TR Datasheet - Page 6

• Manufacturer Part Number: LTC1873EG#TR
• Description: IC REG SW 2PH DUAL SYNC 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC1873EG#TR

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 750kHz
• Duty Cycle: 93%
• Voltage - Supply: 3 V ~ 7 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Frequency-max: 750kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PI FU CTIO S
LTC1873
VID n pin includes an on-chip 40k
series with a diode (see Block Diagram).
V
except the output drivers are powered from this pin. V
should be connected to a low noise power supply voltage
between 3V and 7V and should be bypassed to SGND with
at least a 1 F capacitor in close proximity to the LTC1873.
FB2 (Pin 19): Controller 2 Feedback Input. FB2 should be
connected through a resistor divider network to V
set the ouput voltage. The loop compensation network for
controller 2 also connects to FB2.
COMP2 (Pin 20): Controller 2 Loop Compensation. See
COMP1.
RUN/SS2 (Pin 21): Controller 2 Run/Soft-Start. See RUN/
SS1.
FAULT (Pin 22): Output Overvoltage Fault (Latched). The
FAULT pin is an open-drain output with an internal 10 A
pull-up. If either regulated output voltage rises more than
15% above its programmed value for more than 25 s, the
FAULT output will go high and the entire LTC1873 will be
TEST CIRCUIT
6
CC
U
(Pin 18): Power Supply Input. All internal circuits
U
MEASURED
f
OSC
V
U
FB1
2000pF
pull-up resistor in
2k
0.1 F
2000pF
NC
NC
I
BOOST1
OUT2
BOOST1
TG1
BG1
SW1
I
FCB
VID0:4
RUN/SS1
COMP1
FB1
SENSE
MAX1
Test Circuit 1
CC
V
GND
to
CC
I
CC
LTC1873
PGND
disabled. When FAULT is high, both BG pins will go high,
turning on the bottom MOSFET switches and pulling down
the high output voltage. The LTC1873 will remain latched
in this state until the power is cycled. When FAULT mode
is active, the FAULT pin will be pulled up with an internal
10 A current source. Tying FAULT directly to SGND will
disable latched FAULT mode and will allow the LTC1873 to
resume normal operation when the overvoltage fault is
removed.
PGND (Pin 23): Power Ground. The BG n drivers return to
this pin. Connect PGND to a high current ground node in
close proximity to the sources of external MOSFETs, QB1
and QB2, and the V
SW2 (Pin 24): Controller 2 Switching Node. See SW1.
TG2 (Pin 25): Controller 2 Top Gate Drive. See TG1.
BG2 (Pin 26): Controller 2 Bottom Gate Drive. See BG1.
BOOST2 (Pin 27): Controller 2 Top Gate Driver Supply.
See BOOST1.
I
MAX2
PV
5V
RUN/SS2
BOOST2
COMP2
CC
FAULT
I
I
PVCC
MAX2
SW2
BG2
TG2
FB2
(Pin 28): Controller 2 Current Limit Set. See I
NC
I
BOOST2
2k
2000pF
+
IN
100 F
and V
2000pF
OUT
bypass capacitors.
V
V
FAULT
FB2
1873 TC
MAX1
.