ISL62871HRUZ-T Intersil, ISL62871HRUZ-T Datasheet - Page 13

IC CTRLR DC/DC PWM 16-TQFN

ISL62871HRUZ-T

Manufacturer Part Number
ISL62871HRUZ-T
Description
IC CTRLR DC/DC PWM 16-TQFN
Manufacturer
Intersil
Datasheet

Specifications of ISL62871HRUZ-T

Pwm Type
Controller
Number Of Outputs
1
Frequency - Max
330kHz
Duty Cycle
100%
Voltage - Supply
3.3 V ~ 25 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
-10°C ~ 100°C
Package / Case
16-UTQFN (16-µTQFN)
Frequency-max
330kHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL62871HRUZ-T
Manufacturer:
INTERSIL
Quantity:
20 000
External Setpoint Reference
The IC can use an external setpoint reference voltage as an
alternative to VID-selected, resistor-programmed setpoints.
This is accomplished by removing all setpoint programming
resistors, connecting the SET0 pin to the VCC pin, and
feeding the external setpoint reference voltage to the VID0
pin. When SET0 and VCC are tied together, the following
internal reconfigurations take place:
The converter will now be in regulation when the voltage on
the FB pin equals the voltage on the VID0 pin. As with
resistor-programmed setpoints, the reference voltage range
on the VID0 pin is 500mV to 1.5V. Use Equations 1, 2, and 3
beginning on page 11 should it become necessary to
implement an output voltage-divider network to make the
external setpoint reference voltage compatible with the
500mV to 1.5V constraint.
Soft-Start and Voltage-Step Delay
Circuit Description
When the voltage on the VCC pin has ramped above the
rising power-on reset voltage V
the EN pin has increased above the rising enable threshold
voltage V
and enables the reference amplifier V
current I
pin into the parallel RC network of capacitor C
resistance R
connected R
Equation 17:
The voltage on the SREF pin rises as I
the voltage reference setpoint selected by the state of the
VID inputs at the time the EN pin is asserted. The regulator
controls the PWM such that the voltage on the FB pin tracks
the rising voltage on the SREF pin. Once C
the selected setpoint voltage, the I
out of the 20µA current limit and decays to the static value
set by V
is asserted to when V
reference setpoint is the soft-start delay t
by Equation 18:
R
t
SS
T
- VID0 pin opens its 500nA pull-down current sink
- Reference source selector switch SW4 moves from INT
- VID1 pin is disabled
=
position (internal 500mV) to EXT position (VID0 pin)
=
R
SET1
(
SS
SREF
I
ENTHR
SS
is limited to 20µA and is sourced out of the SREF
T
SET
+
C
. The resistance R
÷
R
SOFT
SET2
R
, the SREF pin releases its discharge clamp
programming resistors and is written as
T
. The elapsed time from when the EN pin
)
+
SREF
LN 1
…R
(
SET n ( )
has reached the voltage
V
----------------------------- -
13
START-UP
I
VCC_THR
SS
T
is the sum of all the series
SS
R
T
SET
current source comes
SS
)
, and the voltage on
SS
. The soft-start
charges C
SOFT
which is given
SOFT
charges to
ISL62871, ISL62872
and
SOFT
(EQ. 17)
(EQ. 18)
to
Where:
The end of soft-start is detected by I
capacitor C
reference setpoint. The SSOK flag is set, the PGOOD pin
goes high, and the I
voltage-step current source I
±100µA. Whenever the VID inputs or the external setpoint
reference, programs a different setpoint reference voltage,
the I
C
the selected setpoint voltage, the I
out of the 100µA current limit and decays to the static value
set by V
the new voltage is called the voltage-step delay t
given by Equation 19:
Where:
Component Selection For C
Choosing the C
particular soft-start delay t
which is written as:
Where:
Choosing the C
particular voltage-step delay t
Equation 21, which is written as:
C
t
C
VS
SOFT
SOFT
SOFT
- I
- V
- R
- I
- V
- V
- R
- t
- I
- V
- R
VS
=
the state of the VID inputs at the time EN is asserted
inputs
from
the state of the VID inputs at the time EN is asserted
SS
VS
SS
SS
START-UP
T
NEW
OLD
T
START-UP
T
(
I
to that new level at ±100µA. Once C
=
current source charges or discharges capacitor
=
is the sum of the R
is the sum of the R
is the sum of the R
SREF
VS
is the soft-start current source at the 20µA limit
is the ±100µA setpoint voltage-step current
is the soft-start delay
is the soft-start current source at the 20µA limit
----------------------------------------------------------------------------- -
---------------------------------------------------------------------
R
is the setpoint voltage that V
R
SOFT
is the new setpoint voltage selected by the VID
C
T
T
SOFT
÷
LN 1
LN 1
SOFT
SOFT
R
is the setpoint reference voltage selected by
is the setpoint reference voltage selected by
charges to the designated V
(
T
(
. The elapsed time to charge C
) LN 1
SS
t
capacitor to meet the requirements of a
capacitor to meet the requirements of a
SS
V
-------------------------------------- -
V
----------------------------- -
t
VS
NEW
START-UP
I
current source changes over to the
(
SS
I ±
VS
SS
SET
SET
SET
(
-------------------------------------------
R
V
VS
is calculated with Equation 20,
V
T
VS
R
NEW
OLD
T
I
programming resistors
programming resistors
programming resistors
VS
)
which has a current limit of
is calculated with
SOFT
VS
)
R
SS
V
T
OLD
current source comes
NEW
tapering off when
Capacitor
)
)
SOFT
is changing
SET
VS
August 14, 2008
charges to
SOFT
voltage
and is
(EQ. 20)
(EQ. 19)
(EQ. 21)
FN6707.0
to

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