NCP4208MNR2G ON Semiconductor, NCP4208MNR2G Datasheet - Page 15

IC CTLR 8PH VR11.1 PMBUS 48-QFN

NCP4208MNR2G

Manufacturer Part Number
NCP4208MNR2G
Description
IC CTLR 8PH VR11.1 PMBUS 48-QFN
Manufacturer
ON Semiconductor
Datasheet

Specifications of NCP4208MNR2G

Applications
Controller, Intel VR11.1
Voltage - Input
4.7 ~ 5.75 V
Number Of Outputs
8
Voltage - Output
0.16 ~ 5 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TQFN Exposed Pad
Output Voltage
0.375 V to 1.6 V
Input Voltage
0.3 V to 6 V
Switching Frequency
1.5 MHz
Operating Temperature Range
0 C to + 85 C
Mounting Style
SMD/SMT
Duty Cycle (max)
100 %
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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maintained to minimize output deviations as well as
providing full power load transients immediately after
exiting a low power state. The number of phases switched on
when PSI is asserted is set using Bits 7:6 of the Manufacturer
Config Register 0x03. Table 7 shows which phases are
enabled for each configuration.
Output Crowbar
components of the supply, the PWM outputs are driven low
(turning on the low−side MOSFETs) when the output
voltage exceeds the upper crowbar threshold. This crowbar
Table 7. Configuration and Enabled Phases
# Phases
Normally
Running
The sequencing into and out of low power operation is
As part of the protection for the load and output
8
7
6
5
4
3
2
1
Code
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
11
11
11
11
11
11
11
11
# Phases
Running
During
PSI
1
2
4
4
1
1
1
1
1
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Divided by:
Current
Limit
4
4
2
2
4
4
2
2
4
3
2
2
4
2
2
2
4
2
2
2
3
2
2
2
2
2
2
2
1
1
1
1
Running
1, 3, 5, 7
1, 3, 5, 7
Phases
1 and 5
1 and 4
1, 3, 5
1, 3, 5
http://onsemi.com
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
action stops once the output voltage falls below the release
threshold of approximately 300 mV.
PWRGD high limit.
as the reverse current builds up in the inductors. If the output
overvoltage is due to a short in the high−side MOSFET, this
action current limits the input supply or blows its fuse,
protecting the microprocessor from being destroyed.
Output Enable and UVLO
current to the controller must be higher than the UVLO
threshold and the EN pin must be higher than its 0.8 V
threshold. This initiates a system startup sequence. If either
UVLO or EN is less than their respective thresholds, the
NCP4208 is disabled. This holds the PWM outputs at
ground and forces PWRGD, ODN and OD1 signals low.
should be connected to the OD inputs of the external drivers
for the phases that are always on. The ODN pin should be
connected to the OD inputs of the external drivers on the
phases that are shut down during low power operation.
Grounding the driver OD inputs disables the drivers such
that both DRVH and DRVL are grounded. This feature is
important in preventing the discharge of the output
capacitors when the controller is shut off. If the driver
outputs are not disabled, a negative voltage can be generated
during output due to the high current discharge of the output
capacitors through the inductors.
12 V supply range. A trade-off can be made between the
power dissipated in the shunt resistor and the UVLO
threshold. Figure 10 shows the typical resistor value needed
to realize certain UVLO voltages. It also gives the maximum
power dissipated in the shunt resistor for these UVLO
voltages.
The value for the crowbar limit follows the programmable
Turning on the low−side MOSFETs pulls down the output
For the NCP4208 to begin switching, the input supply
In the application circuit (see Figure 2), the OD1 pin
The NCP4208 uses a shunt to generate 5.0 V from the
Figure 10. Typical Shunt Resistor Value and Power
400
350
300
250
200
150
Dissipation for Different UVLO Voltage
8
9
10
11
ICC (UVLO)
12
13
14
15
Rshunt
Pshunt
2−0603 Limit
2−0805 Limit
16
0.325
0.3
0.275
0.25
0.225
0.2
0.175

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