LTC1709EG-8 Linear Technology, LTC1709EG-8 Datasheet - Page 26

• Manufacturer Part Number: LTC1709EG-8
• Description: IC REG SW 2PH SYNC STPDWN 36SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1709EG-8

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 1.3 ~ 3.5 V
• Current - Output: 3A
• Voltage - Input: 4 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Frequency - Switching: -

LTC1709-8/LTC1709-9
APPLICATIO S I FOR ATIO
The worst-case RMS ripple current for a single stage
design peaks at an input voltage of twice the output
voltage. The worst-case RMS ripple current for a two stage
design results in peak outputs of 1/4 and 3/4 of input
voltage. When the RMS current is calculated, higher
effective duty factor results and the peak current levels are
divided as long as the currents in each stage are balanced.
Refer to Application Note 19 for a detailed description of
how to calculate RMS current for the single stage switch-
ing regulator. Figures 3 and 4 help to illustrate how the
input and output currents are reduced by using an addi-
tional phase. The input current peaks drop in half and the
frequency is doubled for this 2-phase converter. The input
capacity requirement is thus reduced theoretically by a
factor of four! Ceramic input capacitors with their
unbeatably low ESR characteristics can be used.
Figure 4 illustrates the RMS input current drawn from the
input capacitance vs the duty cycle as determined by the
ratio of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 50%
in a 2-phase solution due to the current splitting between
the two stages.
26
U
U
W
U
An interesting result of the 2-phase solution is that the V
which produces worst-case ripple current for the input
capacitor, V
duces zero input current ripple in the 2-phase design.
The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V
term from the stage that has its bottom MOSFET on
subtracts current from the (V
resulting from the stage which has its top MOSFET on. The
output ripple current is:
where D is duty factor.
The input and output ripple frequency is increased by the
number of stages used, reducing the output capacity
requirements. When V
as illustrated in Figures 3 and 4, very low input and output
ripple currents result.
I
RIPPLE
OUT
2
= V
V
fL
OUT
IN
/2, in the single phase design pro-
IN
1 2
is approximately equal to 2(V
1 2
D
IN
D
- V
1
OUT
OUT
1
D
/L discharge current
)/L charging current
OUT
IN
)