ADP3290JCPZ-RL ON Semiconductor, ADP3290JCPZ-RL Datasheet - Page 13

• Manufacturer Part Number: ADP3290JCPZ-RL
• Description: IC CTLR BUCK SW REG 40-LFCSP
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of ADP3290JCPZ-RL

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 4
• Voltage - Output: 0.5 ~ 1.6 V
• Frequency - Switching: 250kHz ~ 4MHz
• Voltage - Input: 12V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Output Voltage: 0.5 V to 1.6 V
• Output Current: 500 uA
• Input Voltage: - 0.3 V to + 6.3 V
• Supply Current: 25 mA
• Switching Frequency: 450 kHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DVID slew−rates. These can be encountered when the
system does a large single VID step for power state changes,
thus the DVID slew−rate needs to be limited to prevent large
in−rush currents. The SS pin uses a 75 mA current source into
the SS capacitor to do this limiting and typical slew−rates of
10mV/mS are set with the design.
Power−Good Monitoring
via the CSREF pin. The PWRGD pin is an open−drain
output whose high level, when connected to a pullup
resistor, indicates that the output voltage is within the
nominal limits specified based on the VID voltage setting.
PWRGD goes low if the output voltage is outside of this
specified range, if the VID DAC inputs are in no CPU mode,
or if the EN pin is pulled low. PWRGD is blanked during a
DVID event for a period of 250 ms to prevent false signals
during the time the output is changing.
delay time (TD5), based on the DELAY timer. Prior to the
SS voltage reaching the programmed VID DAC voltage and
the PWRGD masking−time finishing, the PWRGD pin is
held low. Once the SS pin is within 100 mV of the
programmed DAC voltage, the capacitor on the DELAY pin
begins to charge. A comparator monitors the DELAY
voltage and enables PWRGD when the voltage reaches
1.7 V. The PWRGD delay time is, therefore, set by a current
of 15 mA, charging a capacitor from 0 V to 1.7 V.
Power State Indicator
power state of the load. If this pin is pulled low, the controller
knows the load is in a low power state and it takes the ODN
signal low, which can be used to disable phases for increased
efficiency.
maintained to minimize output voltage deviations as well as
The ADP3290 also adds the use of the SS pin to limit
The power−good comparator monitors the output voltage
The PWRGD circuitry also incorporates an initial turn−on
The PSI pin is used as an input to determine the operating
The sequencing into and out of low−power operation is
Figure 8. DVID Waveform (by VTT, 0.5 V-1.5V)
1-Vo D0~D2-PWM1~3
http://onsemi.com
13
providing full−power load transients immediately following
exit from a low−power state.
current limit threshold is changed when PSI is pulled low.
The current limit threshold is reduced by 1/N such that the
same per phase average current limit is maintained to protect
the components in the system.
Output Crowbar
the PWM outputs are driven low, which turns on the
low−side MOSFETs when the output voltage exceeds the
upper crowbar threshold. This crowbar action stops once the
output voltage falls below the release threshold of
approximately 375 mV.
as the reverse current builds up in the inductors. If the output
overvoltage is due to a short in the high−side MOSFET, this
action current limits the input supply or blows its fuse,
protecting the microprocessor from being destroyed.
Output Enable and UVLO
current to the controller must be higher than the UVLO
threshold and the EN pin must be higher than its 0.8 V
threshold. This initiates a system startup sequence. If either
One additional feature of the ADP3290 is the internal
To protect the load and output components of the supply,
Turning on the low−side MOSFETs pulls down the output
For the ADP3290 to begin switching, the input supply
Figure 9. PSI Mode Transition Waveform (Io = 25A)
1-Vo, 2-PSI, 3-COMP, 4-TRDET, D0~D2-PWM1~3