IDT88K8483BRI IDT, Integrated Device Technology Inc, IDT88K8483BRI Datasheet - Page 131
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IDT88K8483BRI
Manufacturer Part Number
IDT88K8483BRI
Description
IC SPI-4 EXCHANGE 3PORT 672-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT88K8483BRI.pdf
(162 pages)
Specifications of IDT88K8483BRI
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
88K8483BRI
- Current page: 131 of 162
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External Memory Test Results Register
Auxiliary Early Backpressure Threshold Register
Auxiliary Packet Mode Configuration Register
HSTL Test Register
TEST_DONE
ERROR
EBP_THR
PKT_MODE
HSTL_RX_TEST
IDT IDT88K8483
Field
Field
Field
Field
Table 123 Auxiliary Early Backpressure Threshold Register
Table 125 Auxiliary HSTL Receiver Test Control Register
Table 124 Auxiliary Packet Mode Configuration Register
Table 122 External Memory Test Results Register
R
R
R/W
R/W
R/W
Read /
Read /
Read /
Read /
Write
Write
Write
Write
0:0
0:1
0:0
0:0
0:0-1:5
Bits
Bits
Bits
Bits
1
1
14
1
1
Length
Length
Length
Length
1
0
0x40
0
0
Reset
Reset
Reset
Reset
State
State
State
State
131 of 162
This field indicates the status of the external QDR-II SRAM built-in self test.
0: Test in progress. This bit is set to 0 when the test is triggered by writing 1 to the
field TEST in
1: Test finished.
This field indicates the result of the external QDR-II SRAM test.
0: No error.
1: Some error with memory BIST.
In the PFP to QDR-II path, this field programs the threshold in the QDR-II FIFO at
which backpressure will be generated. If free space in the FIFO is less than this
threshold, backpressure is initiated towards the PFP egress by setting the FIFO sta-
tus to satisfied. This threshold is a global setting that is used by all FIFOs in the
QDR-II SRAM.
This bit controls the mode of transfer from QDR-II to PFP ingress.
0: Cut through mode. In this mode, contiguous transfers from the QDR-II SRAM to
the PFP may contain interleaved packets.
1: Packet mode.In this mode, whole packets are transferred from the QDR-II SRAM
to PFP.
Controls an internal test function in the HSTL receiver.
0: Normal operation
1: Reserved for internal IDT test
(Block Base=
(Block Base=
(Block Base=
(Block Base=
Table
121.
0x0A00
0x0A00
0x0A00
0x0A00
, Register Offset=0x05)
Description
Description
Description
Description
, Register Offset=0x08)
, Register Offset=0x0E)
, Register Offset=0x07)
October 20, 2006
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