IDT88K8483BRI IDT, Integrated Device Technology Inc, IDT88K8483BRI Datasheet - Page 144
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IDT88K8483BRI
Manufacturer Part Number
IDT88K8483BRI
Description
IC SPI-4 EXCHANGE 3PORT 672-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT88K8483BRI.pdf
(162 pages)
Specifications of IDT88K8483BRI
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
88K8483BRI
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PMON Per LID Counter Table
PMON Per Module/Interface Counter Table
SPI4+insert+loop
Individual for A/B
Module A
Module A
Module A
Module B
Module B
Module B
Module B
Module B
IDT IDT88K8483
accumulation
Note: The counter tables are subject to accumulation of data from a point in time to another.
Note: The counter tables are subject to accumulation of data from a point in time to another based on the Timebase.
Subject to
For the measure points please refer to
Length
24
24
24
24
24
24
Note: (1) In the register offset column ‘n’ refers to the LID number, with n between 0 and 63. The register address of the counter for a partic-
ular LID is derived from the offset address using the equation shown in the register offset column and adding it to the block_base.
(2) For the measure point, refer to
Table 155 PMON Per Module/Interface Counter Table (Block Base=0x0E00 Register Offset=0x00-0x10
0x 6n
0x 6n+1
0x6n+2
0x6n+3
0x6n+4
0x6n+5
29
26
8
8
16
16
29
26
8
8
16
16
30
24
24
24
24
Length
Register
Table 154 PMON Per LID Counter Table (Block Base=0x0C00, Register Offset=0x00-0x17F)
Offset
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
Register
Offset
3,4
3,4
13,14
13,14
18,19
8,9
Measure
Point
Figure 33 PMON Measure Points p.67
Figure 33 PMON Measure Points p.67
6,7
3,4
1,2
6,7
21,22
1,2
13,14
12
16,17
16,17
11
12
10
5
20
15
10
Measure
0
0
0
0
0
0
Reset
State
Point
Tributary ingress good packet counter
Tributary ingress abort packet counter
Main ingress good packet counter
Main ingress abort packet counter
Tributary egress packets counter
Main egress packets counter
144 of 162
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
State
T-M too long packet
T-M too short packet
Main SPI-4 ingress byte
M-T too long packet
Auxiliary egress transfer counter
Tributary SPI-4 ingress byte
Tributary SPI-4 ingress transfer
Tributary SPI-4 DIP-2 error
Tributary SPI-4 DIP-4 error
Main SPI-4 ingress transfer
M-T too short packet
Main SPI-4 DIP-2 error
Main SPI-4 DIP-4 error
PRBS bit error
Auxiliary ingress transfer counter
PRBS ingress transfer counter
PRBS egress transfer counter
Description
Description
October 20, 2006
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