MT36LSDF12872G-133D1 Micron Technology Inc, MT36LSDF12872G-133D1 Datasheet - Page 11

• Manufacturer Part Number: MT36LSDF12872G-133D1
• Description: MODULE SDRAM 1GB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36LSDF12872G-133D1

• Memory Type: SDRAM
• Memory Size: 1GB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.466A
• Number Of Elements: 36
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 5:
Burst Type
CAS Latency
Operating Mode
PDF: 09005aef807da15c/Source: 09005aef80f69382
SDF36C64_128x72G.fm - Rev. E 10/05 EN
CAS Latency Diagram
COMMAND
COMMAND
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by BL, the burst type, and the
starting column address, as shown in Table 6 on page 10.
CL is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a read command is registered at T0
and the latency is programmed to two clocks, the DQ will start driving after T1 and the
data will be valid by T2, as shown in Figure 5. Table 7 on page 12 indicates the operating
frequencies at which each CL setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The pro-
grammed BL applies to both read and write bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CL = 2
512MB, 1GB (x72, ECC, DR): 168-Pin SDRAM RDIMM
NOP
NOP
T1
T1
t
t AC
LZ
CL = 3
11
T2
T2
NOP
NOP
t
t AC
D
LZ
t OH
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4
Mode Register Definition
©2003 Micron Technology, Inc. All rights reserved.