MT36LSDF12872G-133D1 Micron Technology Inc, MT36LSDF12872G-133D1 Datasheet - Page 8

• Manufacturer Part Number: MT36LSDF12872G-133D1
• Description: MODULE SDRAM 1GB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36LSDF12872G-133D1

• Memory Type: SDRAM
• Memory Size: 1GB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.466A
• Number Of Elements: 36
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Initialization
Mode Register Definition
Burst Length
PDF: 09005aef807da15c/Source: 09005aef80f69382
SDF36C64_128x72G.fm - Rev. E 10/05 EN
are available for use by the customer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device (DIMM) occur via a standard I
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
SDRAMs must be powered up and initialized in a predefined manner. Operational pro-
cedures other than those specified may result in undefined operation. Once power is
applied to V
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands should be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All device
banks must then be precharged, thereby placing the device in the all device banks idle
state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of BL, a burst type, CL, an operating mode, and a write
burst mode, as shown in Figure 4 on page 9. The mode register is programmed via the
LOAD MODE REGISTER command and will retain the stored information until it is pro-
grammed again or the device loses power.
Mode register bits M0–M2 specify BL, M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify CL, M7 and M8 specify the operating mode, M9 specifies the
write burst mode, and M10 and M11 are reserved for future use. Address A12 (M12) is
undefined but should be driven LOW during loading of the mode register.
The mode register must be loaded when all device banks are idle, and the controller
must wait the specified time before initiating the subsequent operation. Violating either
of these requirements will result in unspecified operation.
Read and write accesses to the SDRAM are burst oriented, with BL being programmable,
as shown in Figure 4. BL determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. BL of 1, 2, 4, or 8 locations are avail-
able for both the sequential and the interleaved burst types, and a full-page burst is
available for the sequential type. The full-page burst is used in conjunction with the
BURST TERMINATE command to generate arbitrary BL.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to BL is effectively
selected. All accesses for that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached, as shown in Table 6 on page 10. The
DD
and V
DD
512MB, 1GB (x72, ECC, DR): 168-Pin SDRAM RDIMM
Q (simultaneously) and the clock is stable (stable clock is
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Initialization
2
C