MT36LSDF12872G-133D1 Micron Technology Inc, MT36LSDF12872G-133D1 Datasheet - Page 4

• Manufacturer Part Number: MT36LSDF12872G-133D1
• Description: MODULE SDRAM 1GB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36LSDF12872G-133D1

• Memory Type: SDRAM
• Memory Size: 1GB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.466A
• Number Of Elements: 36
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 5:
PDF: 09005aef807da15c/Source: 09005aef80f69382
SDF36C64_128x72G.fm - Rev. E 10/05 EN
74–77, 86–89, 91–95, 97–
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
28, 29, 46, 47, 112, 113,
21, 22, 52, 53, 105, 106,
101, 103–104, 139–142,
144, 149–151, 153–156,
33-38, 117-121, 123,
42, 79, 125, 163
30, 45, 114, 129
Pin Number
27, 111, 115
126
130, 131
158–161
136, 137
165-167
39, 122
128
147
83
(1GB)
Pin Descriptions
Pin numbers may not correlate with symbol order; refer to Pin Assignment table on page 3 for more
information
A0–A12
RAS#, CAS#,
DQ0–DQ63
BA0, BA1
CK0–CK3
DQMB0–
SA0–SA2
CB0–CB7
Symbol
(512MB)
S0#–S3#
DQMB7
A0–A11
CKE0–1
REGE
WE#
SCL
(1GB)
Output
Output
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
512MB, 1GB (x72, ECC, DR): 168-Pin SDRAM RDIMM
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK0 is distributed through an on-board PLL to all devices.
CK1–CK3 are terminated.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CK0 signal. Deactivating the clock provides power-down and
SELF REFRESH operations (all device banks idle) or CLOCK
SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and self
refresh modes, where CKE becomes asynchronous until after
exiting the same mode. The input buffers, including CK, are
disabled during power-down and self refresh modes, providing
low standby power.
Chip select: S# enable (registered LOW) and disable (registered
HIGH) the command decoder. All commands are masked when
S# are registered HIGH. S# are considered part of the command
code.
Input/Output mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-clock
latency) when DQMB is sampled HIGH during a READ cycle.
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective device bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET
command.
Serial clock for presence-detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect address inputs: These pins are used to configure
the presence-detect device.
Register enable: REGE permits the DIMM to operate in
“buffered” mode (LOW) or “registered” mode (HIGH).
Data I/Os: Data bus.
Check bits.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
Description
©2003 Micron Technology, Inc. All rights reserved.