MT9HTF6472AY-800D1 Micron Technology Inc, MT9HTF6472AY-800D1 Datasheet - Page 30

• Manufacturer Part Number: MT9HTF6472AY-800D1
• Description: MODULE DDR2 512MB 240-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF6472AY-800D1

• Memory Type: DDR2 SDRAM
• Memory Size: 512MB
• Speed: 800MT/s
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17:
pdf: 09005aef80e6f860, source: 09005aef80e5b799
HTF9C32_64_128x72AG_2.fm - Rev. C 6/05 EN
Parameter/Condition
Operating one device bank active-precharge current;
=
commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Operating one device bank active-read-precharge current; I
BL = 4, CL = CL(I
(I
Address bus inputs are SWITCHING; Data pattern is same as I
Precharge power-down current; All device banks idle;
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
Precharge quiet standby current; All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING.
Precharge standby current; All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING.
Active power-down current; All device banks open;
t
STABLE; Data bus inputs are FLOATING.
Active standby current;
All device banks open;
CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating burst write current; All device banks open, Continuous burst
writes; BL = 4, CL = CL (I
=
inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating burst read current; All device banks open, Continuous burst
reads, I
MAX (I
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Burst refresh current;
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are FLOATING; Data bus inputs are FLOATING.
Operating device bank interleave read current; All device banks
interleaving reads, I
(I
HIGH, S# is HIGH between valid commands; Address bus inputs are STABLE
during DESELECTs; Data bus inputs are SWITCHING; See I
detail.
CK (I
DD
DD
t
t
RC (I
RP (I
),
);
DD
t
t
RCD =
CK =
DD
DD
DD
OUT
); CKE is LOW; Other control and address bus inputs are
); CKE is HIGH, S# is HIGH between valid commands; Address bus
),
),
= 0mA; BL = 4, CL = CL (I
t
t
t
RP =
RAS =
CK (I
t
DDR2 I
Values shown for DDR2 SDRAM components only
RCD (I
DD
t
DD
RP (I
), AL = 0;
t
RAS MIN (I
),
DD
OUT
t
DD
RC =
DD
); CKE is HIGH, S# is HIGH between valid commands;
t
= 0mA; BL = 4, CL = CL (I
CK =
DD
t
); CKE is HIGH, S# is HIGH between valid commands;
CK =
Specifications and Conditions – 1GB
), AL = 0;
t
t
RC(I
CK =
t
CK(I
DD
t
CK (I
DD
256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 SDRAM UDIMM
); CKE is HIGH, S# is HIGH between valid
t
DD
),
CK (I
DD
DD
t
t
),
CK =
RRD =
t
), AL = 0;
); Refresh command at every
RAS =
DD
),
t
CK (I
t
t
RC =
RRD(I
t
RAS MAX (I
DD
t
DD
CK =
t
),
DD
RC (I
), AL =
t
RAS =
),
t
CK =
t
CK (I
t
DD
RCD =
t
CK =
DD
),
t
t
DD
CK =
RCD (I
t
t
DD
t
t
CK (I
RAS MAX (I
7 Conditions for
t
RAS =
CK =
30
),
CK =
DD
),
t
t
RCD(I
RP =
t
4W.
t
CK (I
DD
RAS =
DD
t
Fast PDN Exit
MR[12] = 0
Slow PDN Exit
MR[12] = 1
t
CK (I
OUT
CK (I
t
); CKE is
)-1 x
RAS MIN
t
t
DD
RFC (I
RP(I
DD
= 0mA;
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
); CKE is
t
); CKE is
DD
DD
RAS
t
DD
CK
); CKE
),
),
DD
);
t
t
I
RC
RP
)
DD
Specifications and Conditions
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
1,305
1,620
1,845
2,430
3,060
-667
900
540
585
360
630
63
45
63
1,170
1,305
2,250
2,655
-53E
720
855
369
405
270
450
45
45
45
1,080
1,215
2,160
2,655
-40E
720
855
315
315
225
360
45
45
45
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA