MT9HTF6472AY-800D1 Micron Technology Inc, MT9HTF6472AY-800D1 Datasheet - Page 7

• Manufacturer Part Number: MT9HTF6472AY-800D1
• Description: MODULE DDR2 512MB 240-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF6472AY-800D1

• Memory Type: DDR2 SDRAM
• Memory Size: 512MB
• Speed: 800MT/s
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5:
pdf: 09005aef80e6f860, source: 09005aef80e5b799
HTF9C32_64_128x72AG_2.fm - Rev. C 6/05 EN
Pin Numbers
137, 138, 185, 186, 220, 221
57, 58, 60, 61, 63, 70, 176,
177, 179, 180, 182, 183,
125, 134, 146, 155, 164,
202, 211, 223, 232
54 (1GB), 71, 190
73, 74, 192
196
188,
195
193
52
(1GB)
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 6 for more information
RAS#, CAS#, WE#
(512MB, 1GB)
256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 SDRAM UDIMM
CK0, CK0#,
CK1, CK1#,
DM0–DM8
CK2, CK2#
BA2
BA0, BA1,
Symbol
(256MB)
A0–A12
A0–A13
ODT0
CKE0
S0#
(1GB)
Input
Input
Input
Input
Input
Input
Input
Input
Type
On-Die Termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following pins: DQ, DQS, DQS#, CB,
and DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock Enable: CKE (registered HIGH) activates and CKE
(registered LOW) deactivates clocking circuitry on the DDR2
SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating
mode. CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry, POWER-DOWN exit, output disable, and
for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH
exit. Input buffers (excluding CK, CK#, CKE, and ODT) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_18 input but
will detect a LVCMOS LOW level once V
power-up. After Vref has become stable during the power on
and initialization sequence, it must be maintained for proper
operation of the CKE receiver. For proper self-refresh operation
V
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# provides for external
rank selection on systems with multiple ranks. S# is considered
part of the command code.
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Bank Address Inputs: BA0–BA1/BA2 define to which device bank
an ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0–BA1/BA2 define which mode register including
MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE
command.
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for Read/
Write commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
device bank (A10 LOW, device bank selected by BA0–BA1/BA2)
or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE command.
Input Data Mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that
input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
REF
7
must be maintained to this input.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
Description
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
DD
is applied during first