CDB42L51 Cirrus Logic Inc, CDB42L51 Datasheet - Page 81

• Manufacturer Part Number: CDB42L51
• Description: BOARD EVAL FOR CS42L51 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L51

• Main Purpose: Audio, CODEC
• Embedded: Yes, Other
• Utilized Ic / Part: CS42L51, CS8406, CS8415
• Primary Attributes: Stereo, Digital Audio Transmitter and Receiver
• Secondary Attributes: Graphic User Interface, S/PDIF Interface
• Description/function: Audio CODECs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS42L51
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1005

DS679F1
9. PCB LAYOUT CONSIDERATIONS
9.1
9.2
Power Supply, Grounding
As with any high-resolution converter, the
arrangements if its potential performance is to be realized.
power arrangements, with VA and VA_HP connected to clean supplies. VD, which powers the digital circuit-
ry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via
a ferrite bead. In this case, no additional devices should be powered from VD.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as close to the pins of the
sible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same
side of the board as the
kept away from the DAC_FILT+/ADC_FILT+ and VQ pins in order to avoid unwanted coupling into the mod-
ulators. The DAC_FILT+/ADC_FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be posi-
tioned to minimize the electrical path from DAC_FILT+/ADC_FILT+ and AGND. The CDB42L51 evaluation
board demonstrates the optimum layout and power supply arrangements.
QFN Thermal Pad
The CS42L51 is available in a compact QFN package. The under side of the QFN package reveals a large
metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
In split ground systems, it is recommended that this thermal pad be connected to AGND for best perfor-
mance. The CS42L51 evaluation board demonstrates the optimum thermal pad and via configuration.
CS42L51
to minimize inductance effects. All signals, especially clocks, should be
CS42L51
requires careful attention to power supply and grounding
Figure 1 on page 10
shows the recommended
CS42L51
CS42L51
as pos-
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