STEVAL-ISB005V1 STMicroelectronics, STEVAL-ISB005V1 Datasheet - Page 84

• Manufacturer Part Number: STEVAL-ISB005V1
• Description: BOARD EVAL CHARGER ST7260/L6924D
• Manufacturer: STMicroelectronics
• Type: Battery Managementr

Specifications of STEVAL-ISB005V1

• Main Purpose: Power Management, Battery Charger
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: L6924, ST72F63BK6M1
• Primary Attributes: 1 Cell- Li-Ion / Li-Pol, 5 V (USB Input)
• Secondary Attributes: Powered by Wall Adaptor Also, LED Status Indicators
• Input Voltage: 5 V
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: L6924D, ST7260
• Other names: 497-8428

Serial communications interface (SCI)
13.3.2
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Control register 1 (SCICR1)
Table 39.
SCICR1
Bit
7
6
5
4
3
2
R/W
R8
7
WAKE
Name
SCID
PCE
R8
T8
M
SCICR1 register description
Receive data bit 8
Transmit data bit 8
Disabled for low power consumption
Word length
Wake-Up method
Parity Control Enable
R/W
This bit is used to store the 9th bit of the received word when M = 1.
This bit is used to store the 9th bit of the transmitted word when M = 1.
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and
cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 data bits, 1 Stop bit
1: 1 Start bit, 9 data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both transmission and
reception).
This bit determines the SCI Wake-Up method, it is set or cleared by software.
0: Idle line
1: Address mark
This bit selects the hardware parity control (generation and detection). When the
parity control is enabled, the computed parity is inserted at the MSB position (9th bit
if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set
and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
1: Parity control enabled
T8
6
SCID
R/W
5
R/W
M
4
Function
WAKE
R/W
3
PCE
R/W
2
Reset value:
R/W
PS
1
x000 0000 (x0h)
ST7260xx
R/W
PIE
0