LVDS47/48EVK National Semiconductor, LVDS47/48EVK Datasheet - Page 16

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LVDS47/48EVK

Manufacturer Part Number
LVDS47/48EVK
Description
EVALUATION BOARD FOR LVDS47/48
Manufacturer
National Semiconductor

Specifications of LVDS47/48EVK

Main Purpose
Interface, Digital Cable Driver
Utilized Ic / Part
DS90LV047A, DS90LV048A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Other names
*LVDS47/48EVK
*LVDS47/48EVK/NOPB
LVDS47/48EVK/NOPB
6.1.2 Five Test Cases
Five different test cases are provided on this simple 4 layer FR-4 PCB. Each case is described separately. The five test
cases are shown in Figure 1.
LVDS Channel # 1A: LVDS Line Driver
This test channel provides test points for an isolated driver with a standard 100 Ohm differential termination load. Probe
access for the driver outputs is provided at test points on J5-1 and J5-3. The driver input signal (I1) is terminated with a
50 Ohm termination resistor (RT1) on the bottom side of the PCB.
LVDS Channel # 1B: LVDS Receiver
This test channel provides test points for an isolated receiver. Termination options on the receiver inputs accommodate
either two separate 50 Ohm terminations (RT5 and RT6) (each line to ground) or a 100 Ohm resistor connected across
the inputs (differential). The first option allows for a standard signal generator interface. Input signals are connected at
test points I5 (R
) and I6 (R
). A PCB option for a series 453 Ohm resistor (RS1) is also provided in case 50 Ohm
IN-
IN+
probes are employed on the receiver output signal. The default setting is with two separate 50 Ohm terminations (RT5
and RT6) and without the series 453 Ohm resistor (RS1) for use of high impedance probes. The receiver output signal
may be probed at test point O1.
LVDS Channel # 2: PCB Interconnect
This test channel connects Driver #2 to Receiver #2 via a pure PCB interconnect. A test point interface of the LVDS
signaling is provided at test point J6-1 and J6-3. The driver input signal (I2) is terminated with a 50 Ohm termination
resistor (RT2) on the bottom side of the PCB. The receiver output signal may be probed at test point O2. A PCB option
for a series 453 Ohm resistor (RS2) is also provided in case 50 Ohm probes are employed on the receiver output signal.
The default setting is without the series 453 Ohm resistor for use of high impedance probes. A direct probe connection is
possible with a TEK P6247 differential probe high impedance probe (>1GHz bandwidth) on the LVDS signals at test
points J6-1 and J6-3. This channel may be used for analyzing the LVDS signal without the bandwidth limiting effects of
a cable interconnect.
LVDS Channel # 3: Cable Interconnect
This test channel connects Driver #3 to Receiver #3 via the cable interconnect. A test point interface is provided at the
receiver input side of the cable. The driver input signal (I3) is terminated with a 50 Ohm termination resistor (RT3) on
the bottom side of the PCB. LVDS signals are probed via test points on J7. The receiver output signal may be probed at
test point O3. A PCB option for a series 453 Ohm resistor (RS3) is also provided in case 50 Ohm probes are employed
on the receiver output signal (see options section). The default setting is without the series 453 Ohm resistor for use of
high impedance probes. A differential probe connection is possible with a TEK P6247 differential probe (>1GHz
bandwidth) on the LVDS signals at test point J7-1 and J7-3.
LVDS Channel # 4: Cable Interconnect
This test channel connects Driver #4 to Receiver #4 also via the cable interconnect. A test point interface is provided at
the receiver input side of the cable. The driver input signal (I4) is terminated with a 50 Ohm termination resistor (RT4)
on the bottom side of the PCB. LVDS signals are probed via test points on J8. The receiver output signal may be probed
at test point O4. A PCB option for a series 453 Ohm resistor (RS4) is also provided in case 50 Ohm probes are employed
on the receiver output signal. The default setting is without the series 453 Ohm resistor for use of high impedance
probes. A differential probe connection is possible with a TEK P6247 differential probe (>1 GHz bandwidth) on the
LVDS signals at test point J8-1 and J8-3. This channel duplicates channel #3 so that it may be used for a clock function
or for cable crosstalk measurements.

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