LVDS47/48EVK National Semiconductor, LVDS47/48EVK Datasheet - Page 24

• Manufacturer Part Number: LVDS47/48EVK
• Description: EVALUATION BOARD FOR LVDS47/48
• Manufacturer: National Semiconductor

Specifications of LVDS47/48EVK

• Main Purpose: Interface, Digital Cable Driver
• Utilized Ic / Part: DS90LV047A, DS90LV048A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: *LVDS47/48EVK; *LVDS47/48EVK/NOPB; LVDS47/48EVK/NOPB

Option 3: Disabling the LVDS Receiver
The quad receiver features a ganged enable (same as the driver). An active high or an active low are provided. On the
evaluation PCB, the active low input (EN*) is routed to ground. The active high input (EN) is routed to a jumper (J4).
The jumper provides a connection to the V
connect the jumper to the power plane, to disable the receiver connect the jumper to ground.
Option 4: Cables
Different cables may also be tested (different lengths, materials, constructions). A standard RJ45 8-pin connector/pinout
has been used (J1 and J2). Simply plug in the RJ45 1 meter or 5 meter cables included in the kit or build a custom cable.
Option 5: SMA or SMB Connectors
Both SMA and SMB connectors will fit the footprint on the boards for the driver inputs I1-4, receiver outputs O1-4 and
the single receiver inputs I5-6. The board is loaded with SMBs on I4 and O4.
Option 6: Receiver Termination (Channel #1B)
The separate receiver input signals can be terminated separately (50 Ohm on each line to ground) utilizing pads RT5
(inverting to ground) and RT6 (true input to ground) for a signal generator interface. In addition, a single 100 Ohm
differential resistor (across pads RT5 and RT6) can be used if the device is to be driven by a differential driver. Be sure
to remove the 50 Ohm termination resistors RT5 and RT6 if you plan to use the 100 Ohm differential resistor.
6.1.8 Plug & Play
The following simple steps should be taken to begin testing on your completed evaluation board:
1) Connect signal common (Ground) to the pierced lug terminal marked GND
2) Connect the power supply lead to the pierced lug terminal marked VCC (3.3V)
3) Set J3 & J4 jumpers to the power plane (“ON”) to enable the drivers and receivers
4) Connect enclosed RJ45 cable between connectors J1 and J2.
5) Connect a signal generator to the driver input (I4) with:
5) Connect differential probes to test points J8-1 and J8-3
6) View LVDS signals using the same voltage offset and volts/div settings on the scope with the TEK P6247 differential
probes. View the output signal on a separate channel from test point O4. The signals that you will see should resemble
Figure 5.
6.1.9 Common Mode Noise
When the receiver (DS90LV048A) is enabled, a small amount of common mode noise is passed from the output of the
receiver to the inputs as shown in Figure 10. This noise shows up on the single-ended waveforms, but does not impact
the differential waveform that carries the data. A design improvement was made to the DS90LV048A to reduce the
magnitude of the noise coupled back to the inputs, reducing the feedback by 30% compared to prior devices. This noise
will not be observed if the receiver device is disabled by setting J4 to “OFF” as shown in Figure 11.
a) frequency = 50 MHz (100 Mbps)
b) V
c) t
d) duty cycle = 50% (square wave)
r
& t
IL
= 0V & V
f
= ns
IH
= 3.0V
CC
plane (“ON”) or to the Ground plane (“OFF”). To enable the receiver,