LVDS47/48EVK National Semiconductor, LVDS47/48EVK Datasheet - Page 19

• Manufacturer Part Number: LVDS47/48EVK
• Description: EVALUATION BOARD FOR LVDS47/48
• Manufacturer: National Semiconductor

Specifications of LVDS47/48EVK

• Main Purpose: Interface, Digital Cable Driver
• Utilized Ic / Part: DS90LV047A, DS90LV048A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: *LVDS47/48EVK; *LVDS47/48EVK/NOPB; LVDS47/48EVK/NOPB

LVDS signals should be kept away from CMOS logic signals to minimize noise coupling from the large swing CMOS
signals. This has been accomplished on the PCB by routing CMOS signals on a different signal layer (bottom) than the
LVDS signals (top) wherever possible. If they are required on the same layer, a CMOS signal should never be routed
within three times (3S) the distance between the differential pair (S). Adjacent differential pairs should be at least 2S
away also.
Bypassing capacitors are recommended for each package. A 0.1 µF is sufficient on the quad driver or receiver device
(CB1 and CB2) however, additional smaller value capacitors may be added (i.e. 0.001 µF at CB21 and CB22) if desired.
Traces connecting V
to reduce inductance. Bulk bypassing is provided (CBR1, close by) at the main power connection as well. Additional
power supply high frequency bypassing can be added at CB3, CB13, and CB23 if desired.
6.1.5 Sample Waveforms from the LVDS Evaluation PCB
Single-ended signals are measured from each signal (true and inverting signals) with respect to ground. The receiver
ideally switches at the crossing point of the two signals. LVDS signals have a V
with a typical V
between 1.0 V (V
1 (inverting) signal from the Jx-3 (true) signal. V
so the differential swing (V
differential waveforms are shown in Figure 4.
Figure 4: Single-ended & Differential Waveforms
Pair 1
A
Figure 3: Pair Spacing for Differential Lines
Differential Waveform
Single-Ended Waveforms
OS
OL
B
of 1.2V. Our devices have a typical V
) and 1.4 V (V
CC
and ground should be wide (low impedance, not 50 Ohm dimensions) and employ multiple vias
W
SS
V
) is twice the V
OD
V
Pair 2
OD
A
V
SS
OH
) for a 400 mV V
>2S
B
-V
OD
OD
A = 1.4V V
+100mV
0V Differential (+1.2V)
-100mV
B = 1.0V V
Ground
A – B = 0V
magnitude. Drawn single-ended waveforms and the corresponding
OD
TTL/CMOS
= (Jx-3) – (Jx-1). The V
S
OD
. The differential waveform is constructed by subtracting the Jx-
OH
OL
OD
of 300mV, but for the example below, we will use a signal
>3S
OD
magnitude is either positive or negative,
OD
specification of 250mV to 450mV