LM8333EVALKIT National Semiconductor, LM8333EVALKIT Datasheet - Page 11

• Manufacturer Part Number: LM8333EVALKIT
• Description: BOARD EVALUATION LM8333
• Manufacturer: National Semiconductor

Specifications of LM8333EVALKIT

• Main Purpose: Interface, Special Purpose
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: LM8333
• Primary Attributes: Mobile I/O Companion with Key-Scan, I/O Expansion, PWM, Access.bus Host
• Secondary Attributes: Board has MCU for USB to PC GUI
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9.6 WAKE-UP FROM HALT MODE
Any bus transaction initiated by the host may encounter the
LM8333 device in Halt mode or busy with processing data,
such as controlling the FIFO buffer or executing interrupt ser-
vice routines.
Figure 10
while the LM8333 is in Halt mode (CPU clock is stopped). Any
activity on the ACCESS.bus wakes up the LM8333, but it
cannot acknowledge the first bus cycle immediately after
wake-up.
The host drives a Start condition followed by seven address
bits and a R/W bit. The host then releases SDA for one clock
period, so that it can be driven by the LM8333.
If the LM8333 does not drive SDA low during the high phase
of the clock period immediately after the R/W bit, the bus cycle
shows the case in which the host sends a command
FIGURE 10. LM8333 Responds with NACK, Host Retries Command
FIGURE 9. Host Read Command
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terminates without being acknowledged (shown as NACK in
Figure
a Stop condition. After aborting the bus cycle, the host may
then retry the bus cycle. On the second attempt, the LM8333
will be able to acknowledge the slave address, because it will
be in Active mode.
Alternatively, the I
byte (00000001), which will not be acknowledged by any de-
vice. This byte can be used to wake up the LM8333 from Halt
mode.
The LM8333 may also stall the bus transaction by pulling the
SCL low, which is a valid behavior defined by the I
fication.
10). The host then aborts the transaction by sending
2
C specification allows sending a START
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2
C speci-