LM8333EVALKIT National Semiconductor, LM8333EVALKIT Datasheet - Page 6

• Manufacturer Part Number: LM8333EVALKIT
• Description: BOARD EVALUATION LM8333
• Manufacturer: National Semiconductor

Specifications of LM8333EVALKIT

• Main Purpose: Interface, Special Purpose
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: LM8333
• Primary Attributes: Mobile I/O Companion with Key-Scan, I/O Expansion, PWM, Access.bus Host
• Secondary Attributes: Board has MCU for USB to PC GUI
• Lead Free Status / RoHS Status: Not applicable / Not applicable

www.national.com
The LM8333 will remain in Active mode as long as a key
event, or any other event, which causes the IRQ output to be
asserted is not resolved.
8.4.1 ACCESS.bus Activity
When the LM8333 is in Halt mode, any activity on the
ACCESS.bus interface will cause the LM8333 to exit from
Halt mode. However, the LM8333 will not be able to acknowl-
edge the first bus cycle immediately following wake-up from
Halt mode. It will respond with a negative acknowledgement,
and the host should then repeat the cycle.
The LM8333 will be prevented from entering Halt mode if it
shares the bus with peripherals that are continuously active.
For lowest power consumption, the LM8333 should only
share the bus with peripherals that require little or no bus ac-
tivity after system initialization.
8.5 KEYPAD SCANNING
The LM8333 starts new scanning cycles at fixed time intervals
of about 4 ms. If a change in the state of the keypad is de-
tected, the keypad is rescanned after a debounce delay.
When the state change has been reliably captured, it is en-
coded and written to the FIFO buffer.
If more than two keys are pressed simultaneously, the pattern
of key closures may be ambiguous, so pressing more than
two keys asserts the Error Flag condition and the IRQ output
(if enabled). The host may attempt to interpret the events
stored in the FIFO or discard them.
The SF keys connect the WAKE_INx pins directly to ground.
There can be up to eight SF-keys. If any of these keys are
pressed, other key presses that use the same WAKE_INx pin
will be ignored.
8.6 COMMUNICATION INTERFACE
The two-wire ACCESS.bus interface is used to communicate
with a host. The ACCESS.bus interface is fully compliant with
the I
speeds up to 400 kHz.
An ACCESS.bus transfer starts with a byte that includes a 7-
bit slave device address. The LM8333 responds to a fixed
device address. This address is 0xA2, when aligned to the
The codes are loaded into the FIFO buffer in the order in
which they occurred.
WAKE_IN0
WAKE_IN1
WAKE_IN2
WAKE_IN3
WAKE_IN4
WAKE_IN5
WAKE_IN6
WAKE_IN7
2
Cbus standard. The LM8333 operates as a bus slave at
K_OUT0
Table 2
0x01
0x11
0x21
0x31
0x41
0x51
0x61
0x71
shows an example sequence of
K_OUT1
0x02
0x12
0x22
0x32
0x42
0x52
0x62
0x72
TABLE 1. Keypad Matrix Code Assignments
K_OUT2 K_OUT3
0x03
0x13
0x23
0x33
0x43
0x53
0x63
0x73
0x04
0x14
0x24
0x34
0x44
0x54
0x64
0x74
6
K_OUT4
MSB (7-bit address mapped to bits 7:1, rather than bits 6:0).
Bit 0 is a direction bit (0 on write, 1 on read).
Because it is a slave, the LM8333 never initiates an
ACCESS.bus cycle, it only responds to bus cycles initiated by
the host. The LM8333 may signal events to the host by as-
serting the IRQ interrupt request.
8.6.1 Interrupts Between the Host and LM8333
The IRQ output is used to signal unresolved interrupts, errors,
and key-events to the host.
The host can use an available GEN_IO_0 or GEN_IO_1 pin
to interrupt (or wake-up) the LM8333, if it is not being used for
another function. The host can also wake-up the LM8333 by
sending a Start Condition on the ACCESS.bus interface.
Note: The LM8333 it will not be able to acknowledge the first byte received
8.6.2 Interrupt Sources
The IRQ output is asserted on these conditions:
•
•
•
The IRQ output remains asserted until the interrupt code is
read.
9.0 Device Operation
9.1 EVENT CODE ASSIGNMENT
After power-on reset, the LM8333 starts scanning the keypad.
It stays active for a default time of about 500 ms after the last
key is released, after which it enters a standby mode to min-
imize power consumption (<2 µA standby current).
Table 1
coded by the hardware. Key-press events are assigned the
codes listed in
released, the MSB of the code is clear.
events, and
codes loaded into the FIFO buffer.
0x05
0x15
0x25
0x35
0x45
0x55
0x65
0x75
Any new key-event.
Any error condition, which is indicated by the error code.
Any enabled interrupt on either of the GEN_IO_0 or
GEN_IO_1 pins that can be configured as external
interrupt inputs. When enabled, any rising or falling edge
triggers an interrupt.
from the host after wake-up. In this case, the host will have to resend
the slave address.
lists the codes assigned to the matrix positions en-
K_OUT5
Figure 2
0x06
0x16
0x26
0x36
0x46
0x56
0x66
0x76
Table
1, but with the MSB set. When a key is
shows the resulting sequence of event
K_OUT6
0x07
0x17
0x27
0x37
0x47
0x57
0x67
0x77
K_OUT7
0x08
0x18
0x28
0x38
0x48
0x58
0x68
0x78
SF Keys
0x09
0x19
0x29
0x39
0x49
0x59
0x69
0x79