LM8333EVALKIT National Semiconductor, LM8333EVALKIT Datasheet - Page 16

• Manufacturer Part Number: LM8333EVALKIT
• Description: BOARD EVALUATION LM8333
• Manufacturer: National Semiconductor

Specifications of LM8333EVALKIT

• Main Purpose: Interface, Special Purpose
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: LM8333
• Primary Attributes: Mobile I/O Companion with Key-Scan, I/O Expansion, PWM, Access.bus Host
• Secondary Attributes: Board has MCU for USB to PC GUI
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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Internal Oscillator
System Oscillator (mclk)
System Oscillator and Internal Frequency
Variation
Input Pulse Width Low
Input Pulse Width High
ACCESS Bus Input Signals:
Condition (I
ACCESS Bus Output Signals
13.0 AC Electrical Characteristics
(Temperature: -40°C
Data sheet specification limits are guaranteed by design, test, or statistical analysis.
Bus Free time Between Stop and Start
SCL Setup Time (t
SCL Hold Time (t
SCL Setup Time (t
Data High Setup Time (t
Data Low Setup Time (t
SCL Low Time (t
SCL High Time (t
SDA Hold Time (t
SDA Setup Time (t
SDA Hold Time (t
Note 7: Guaranteed by design, test, or statistical analysis.
Note 8: The ACCESS.bus interface implements and meets the timing necessary for interface to the I
are designed with open-drain output as required for bidirectional operation. Due to System Oscillator (mclk) Variation, this specification may not meet the AC
timing and current/voltage drive requirements of the full bus specification.
BUFI
)
(Note
Parameter
SCLlowi
CSTR
SCLhighi
SDAhi
SDAho
CSTO
CSTR
SDAsi
7,
≤
hi)
)
)
)
Note
si)
si)
)
T
(Note
DLCsi
)
(Note
(Note
DHCsi
(Note
A
(Note
(Note
(Note
(Note
≤
)
8)
+85°C)
)
(Note
7)
7)
(Note
7)
7,
7,
7,
7,
7,
FIGURE 12. ACCESS.bus Start and Stop Condition Timing
Note
Note
Note
Note
Note
7,
7,
Note
8)
8)
Note
8)
8)
8)
8)
8) Before SCL Rising Edge (RE)
External R from CLK_IN to GND
(R = 68 kΩ)
2.25V
External R from CLK_IN to GND
(R = 68 kΩ)
2.25V
2.25V
Before Stop Condition
After Stop Condition
Before Start Condition
Before SCL RE
After SCL Falling Edge (FE)
After SCL RE
After SCL FE
Before SCL RE
After SCL FE
≤
≤
≤
V
V
V
CC
CC
CC
≤
≤
≤
Conditions
16
2.75V
2.75V
2.75V
2
C bus and SMBus protocol at logic levels. The bus drivers
(Note
Min
0.7
0.7
16
12
12
8
8
8
2
2
0
2
7
7)
0.75
Typ
75
(Note
Max
±30
7)
20210614
Units
mclk
mclk
µs
ns
µs
%