EVAL-AD5425EBZ Analog Devices Inc, EVAL-AD5425EBZ Datasheet - Page 3

• Manufacturer Part Number: EVAL-AD5425EBZ
• Description: BOARD EVALUATION FOR AD5425
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5425EBZ

• Number Of Dac's: 1
• Number Of Bits: 8
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 2.47M
• Data Interface: Serial
• Settling Time: 15ns
• Dac Type: Current
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 125°C
• Utilized Ic / Part: AD5425
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPECIFICATIONS
V
otherwise noted. DC performance measured with OP177, ac performance with AD8038, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
REFERENCE INPUT
DIGITAL INPUT/OUTPUT
DYNAMIC PERFORMANCE
DD
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
Output Leakage Current
Reference Input Range
V
R
Input Capacitance
Input High Voltage, V
Input Low Voltage, V
Output High Voltage, V
Output Low Voltage, V
Input Leakage Current, I
Input Capacitance
Reference Multiplying Bandwidth
Output Voltage Settling Time
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Output Capacitance
Digital Feedthrough
Analog THD
REF
FB
= 2.5 V to 5.5 V, V
Code Zero Scale
Code Full Scale
I
I
Measured to ±1 mV
Measured to ±4 mV
Measured to ±16 mV
OUT
OUT
Resistance
Input Resistance
1
2
1
REF
IL
IH
1
OL
OH
1
= 10 V, I
IL
OUT
2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T
Min
8
8
1.7
V
V
DD
DD
− 1
− 0.5
Typ
±5
±10
10
10
3
5
4
10
90
55
50
40
15
2
70
48
12
25
22
10
0.1
81
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Max
8
±0.25
±0.5
±10
±10
±20
12
12
6
8
0.6
0.4
0.4
1
10
160
110
100
75
30
17
30
25
12
Unit
Bits
LSB
LSB
mV
ppm FSR/°C
nA
nA
V
kΩ
kΩ
pF
pF
V
V
V
V
V
V
μA
pF
MHz
ns
ns
ns
ns
ns
nV-s
dB
dB
pF
pF
pF
pF
nV-s
dB
Conditions/Comments
Guaranteed monotonic
Data = 0x0000, T
Data = 0x0000, T = −40°C to +125°C, I
Input resistance TC = −50 ppm/°C
Input resistance TC = −50 ppm/°C
V
V
V
V
V
V
alternately loaded with 0s and 1s
Interface delay time
Rise and fall time, V
1 LSB change around major carry V
DAC latch loaded with all 0s. V
1 MHz
10 MHz
All 0s loaded
All 1s loaded
All 0s loaded
All 1s loaded
Feedthrough to DAC output with SYNC high
and alternate loading of all 0s and all 1s
V
DD
DD
DD
DD
REF
REF
REF
= 4.5 V to 5 V, I
= 2.5 V to 3.6 V, I
= 4.5 V to 5 V, I
= 2.5 V to 3.6 V, I
= ±3.5 V, DAC loaded all 1s
= ±3.5 V, R
= 3.5 V p-p; all 1s loaded, f = 1 kHz
LOAD
A
= 25°C, I
SOURCE
SINK
= 100 Ω, DAC latch
REF
SOURCE
SINK
= 200 μA
= 10 V, R
= 200 μA
= 200 μA
MIN
= 200 μA
OUT
to T
1
REF
LOAD
MAX
= ±3.5 V
= 100 Ω
REF
AD5425
, unless
OUT
= 0 V
1