OM11048 NXP Semiconductors, OM11048 Datasheet - Page 45

• Manufacturer Part Number: OM11048
• Description: BOARD LPCXPRESSO LPC1343
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor
• Type: MCUr

Specifications of OM11048

• Contents: Board, Software
• Processor To Be Evaluated: LPC1343
• Processor Series: LPC13xx
• Interface Type: USB, I2C, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Tool Type: Demonstration Board
• Core Architecture: ARM
• Cpu Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: LPC1343
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4947

NXP Semiconductors
[8]
[9]
[10] A Fast-mode I
LPC1311_13_42_43
Product data sheet
Fig 22. I
The maximum t
t
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
t
acknowledge.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
Standard-mode I
VD;ACK
SU;DAT
SDA
SCL
is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
2
by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t
C-bus pins clock timing
70 %
30 %
S
2
t
C-bus device can be used in a Standard-mode I
f
HD;DAT
2
C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
t
f
could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of t
70 %
30 %
1 / f
SCL
t
HD;DAT
70 %
30 %
70 %
30 %
All information provided in this document is subject to legal disclaimers.
t
SU;DAT
Rev. 3 — 10 August 2010
70 %
30 %
2
C-bus system but the requirement t
t
LOW
r(max)
t
HIGH
+ t
32-bit ARM Cortex-M3 microcontroller
70 %
30 %
SU;DAT
LPC1311/13/42/43
t
VD;DAT
= 1000 + 250 = 1250 ns (according to the
SU;DAT
= 250 ns must then be met.
© NXP B.V. 2010. All rights reserved.
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LOW
VD;DAT
45 of 62
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or