EVAL-ADUC847QSZ Analog Devices Inc, EVAL-ADUC847QSZ Datasheet - Page 86

• Manufacturer Part Number: EVAL-ADUC847QSZ
• Description: KIT DEV QUICK START FOR ADUC847
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC847QSZ

• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: 8051
• Silicon Core Number: ADuC847
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC847
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC845/ADuC847/ADuC848
IEIP2—Secondary Interrupt Enable Register
SFR Address:
Power-On Default:
Bit Addressable:
Table 60. IEIP2 Bit Designations
Bit No.
7
6
5
4
3
2
1
0
INTERRUPT PRIORITY
The interrupt enable registers are written by the user to enable
individual interrupt sources; the interrupt priority registers
allow the user to select one of two priority levels for each
interrupt. A high priority interrupt can interrupt the service
routine of a low priority interrupt, and if two interrupts of
different priorities occur at the same time, the higher level
interrupt is serviced first. An interrupt cannot be interrupted by
another interrupt of the same priority level. If two interrupts of
the same priority level occur simultaneously, the polling
sequence, as shown in Table 61, is observed.
Table 61. Priority within Interrupt Level
Source
PSMI
WDS
IE0
RDY0/RDY1
TF0
IE1
TF1
ISPI/I2CI
RI/TI
TF2/EXF2
TII
Name
----
PTI
PPSM
PSI
----
ETI
EPSMI
ESI
1 (Highest)
2
2
3
4
5
6
7
8
9
11 (Lowest)
Priority
Description
Not Implemented. Write Don’t Care.
Time Interval Counter Interrupt Priority Setting (1 = High, 0 = Low).
Power Supply Monitor Interrupt Priority Setting (1 = High, 0 = Low).
SPI/I
This bit must contain 0.
Set by the user to enable the time interval counter interrupt.
Cleared by the user to disable the time interval counter interrupt.
Set by the user to enable the power supply monitor interrupt.
Cleared by the user to disable the power supply monitor interrupt.
Set by the user to enable the SPI/I
Cleared by the user to disable the SPI/I
A9H
A0H
No
2
C Interrupt Priority Setting (1 = High, 0 = Low).
Description
Power Supply Monitor Interrupt
Watchdog Timer Interrupt
External Interrupt 0
ADC Interrupt
Timer/Counter 0 Interrupt
External Interrupt 1
Timer/Counter 1 Interrupt
SPI/I
UART Serial Port Interrupt
Timer/Counter 2 Interrupt
Timer Interval Counter Interrupt
2
C Interrupt
2
C serial port interrupt.
2
C serial port interrupt.
Rev. B | Page 86 of 108
INTERRUPT VECTORS
When an interrupt occurs, the program counter is pushed onto
the stack, and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in Table 62.
Table 62. Interrupt Vector Addresses
Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
RDY0/RDY1 (ADuC845 only)
ISPI/I2CI
PSMI
TII
WDS
Vector Address
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
0053H
005BH