C8051F336DK Silicon Laboratories Inc, C8051F336DK Datasheet - Page 102
C8051F336DK
Manufacturer Part Number
C8051F336DK
Description
DEV KIT FOR C8051F336
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F336DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F33x
Interface Type
USB, UART
Operating Supply Voltage
7 V to 15 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F336
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1430
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C8051F336/7/8/9
17.2. Power-Fail Reset / V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 17.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The V
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V
V
Important Note: If the V
is selected as a reset source. Selecting the V
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
state is shown below:
1. Enable the V
2. If necessary, wait for the V
3. Select the V
See Figure 17.2 for V
monitor reset. See
istics of the V
102
DD
monitor will still be disabled after the reset.
DD
DD
DD
monitor.
RST
monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
Section “6. Electrical Characteristics” on page 27
monitor (VDMEN bit in VDM0CN = ‘1’).
, the CIP-51 will be released from the reset state. Note that even though internal data
DD
DD
monitor timing; note that the power-on-reset delay is not incurred after a V
monitor is being turned on from a disabled state, it should be enabled before it
DD
monitor to stabilize.
DD
DD
Monitor
monitor is disabled by code and a software reset is performed, the
DD
monitor and configuring it as a reset source from a disabled
DD
monitor as a reset source before it is enabled and stabi-
Rev.1.0
DD
to drop below V
for complete electrical character-
RST
, the power supply
DD
dropped below
DD
returns
DD
DD
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