C8051F336DK Silicon Laboratories Inc, C8051F336DK Datasheet - Page 124

• Manufacturer Part Number: C8051F336DK
• Description: DEV KIT FOR C8051F336
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F336DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: USB, UART
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F336
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1430

C8051F336/7/8/9
20.3. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 20.4) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that
are to be used for analog input, dedicated functions, or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.3 and/or
P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC or IDAC is configured to use the external
conversion start signal (CNVSTR), and any selected ADC or Comparator inputs. The Crossbar skips
selected pins as if they were already assigned, and moves to the next unassigned pin.
Figure 20.4 shows all of the potential peripheral-to-pin assignments available to the crossbar. Note that
this does not mean any peripheral can always be assigned to the highlighted pins. The actual pin assign-
ments are determined by the priority of the enabled peripherals.
124
SF Signals
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
SF Signals
1
Figure 20.4. Crossbar Priority Decoder - Possible Pin Assignments
VREF IDA
Port pin potentially available to peripheral
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the Crossbar must be
manually configured to skip their corresponding port pins.
0
1
x1
2
x2
3
P0
4
5
CNVSTR
6
7
Rev.1.0
0
1
2
Notes:
1. NSS is only pinned out in 4-wire SPI Mode
2. Pins P2.1-P2.4 only on QFN24 Package
3. Pin 2.0 unavailable on crossbar in QFN20 Package
3
P1
4
5
6
7
0
1
2
P2
2
2
3
2
4
2