C8051F336DK Silicon Laboratories Inc, C8051F336DK Datasheet - Page 176

• Manufacturer Part Number: C8051F336DK
• Description: DEV KIT FOR C8051F336
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F336DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: USB, UART
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F336
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1430

C8051F336/7/8/9
SFR Definition 23.3. SPI0CKR: SPI0 Clock Rate
SFR Address = 0xA2
SFR Definition 23.4. SPI0DAT: SPI0 Data
SFR Address = 0xA3
176
Name
Reset
Name
Reset
7:0
7:0
Bit
Bit
Type
Type
Bit
Bit
SPI0DAT[7:0] SPI0 Transmit and Receive Data.
SCR[7:0]
Name
Name
7
0
7
0
SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
f
f
f
SCK
SCK
SCK
6
0
6
0
=
=
=
---------------------------------------------------------- -
2
------------------------- -
2
200kHz
2000000
×
×
(
(
5
0
5
0
SPI0CKR[7:0]
4
+
SYSCLK
1
)
Rev.1.0
4
0
4
SPI0DAT[7:0]
0
SCR[7:0]
R/W
R/W
+
1
)
Function
Function
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0