C8051F336DK Silicon Laboratories Inc, C8051F336DK Datasheet - Page 40

DEV KIT FOR C8051F336

C8051F336DK

Manufacturer Part Number
C8051F336DK
Description
DEV KIT FOR C8051F336
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F336DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F33x
Interface Type
USB, UART
Operating Supply Voltage
7 V to 15 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F336
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1430
C8051F336/7/8/9
7.2.3. Settling Time Requirements
A minimum tracking time is required before each conversion to ensure that an accurate conversion is per-
formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the
the ADC0 sampling capacitance, and the accuracy required for the conversion. Note that in low-power
tracking mode, three SAR clocks are used for tracking at the start of every conversion. For many applica-
tions, these three SAR clocks will meet the minimum tracking time requirements.
Figure 7.3 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice
that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a
given settling accuracy (SA) may be approximated by Equation 7.1. When measuring the Temperature
Sensor output or V
teristics” on page 27
sampling capacitor values.
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (10).
40
TOTAL
is the sum of the AMUX0 resistance and any external source resistance.
Px.x
Px.x
RC
Differential Mode
MUX Select
MUX Select
Input
DD
= R
MUX
with respect to GND, R
Equation 7.1. ADC0 Settling Time Requirements
for ADC0 minimum settling time requirements as well as the mux impedance and
* C
R
R
Figure 7.3. ADC0 Equivalent Input Circuits
SAMPLE
MUX
MUX
t
=
ln
C
C
SAMPLE
SAMPLE
------ -
SA
2
n
TOTAL
×
R
Rev.1.0
TOTAL
reduces to R
C
Px.x
SAMPLE
MUX
Single-Ended Mode
RC
MUX Select
Input
. See
= R
MUX
Section “6. Electrical Charac-
* C
R
SAMPLE
MUX
C
SAMPLE

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