MPC8360E-RDK Freescale Semiconductor, MPC8360E-RDK Datasheet - Page 94

BOARD REFERENCE DESIGN FOR MPC

MPC8360E-RDK

Manufacturer Part Number
MPC8360E-RDK
Description
BOARD REFERENCE DESIGN FOR MPC
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II™ PROr
Type
MPUr
Datasheets

Specifications of MPC8360E-RDK

Contents
Board, Cables, CD, Power Supply
Processor To Be Evaluated
MPC8360E
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB
Operating Supply Voltage
1.3 V
For Use With/related Products
MPC8360E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Clocking
The RCWL[CEVCOD] denotes the QUICC Engine Block PLL VCO internal frequency as shown in
Table
The QUICC Engine block VCO frequency is derived from the following equations:
94
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
75.
ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)
QE VCO Frequency = ce_clk × VCO divider × (1 + CEPDF)
The VCO divider (RCWL[CEVCOD]) must be set properly so that the
QUICC Engine block VCO frequency is in the range of 600–1400 MHz.
The QUICC Engine block frequency is not restricted by the CSB and core
frequencies. The CSB, core, and QUICC Engine block frequencies should
be selected according to the performance requirements.
Table 74. QUICC Engine Block PLL Multiplication Factors (continued)
Note:
1. Reserved modes are not listed.
RCWL[CEPMF] RCWL[CEPDF]
01011
01101
01111
10001
10011
10101
10111
11001
11011
11101
Table 75. QUICC Engine Block PLL VCO Divider
RCWL[CEVCOD]
1
1
1
1
1
1
1
1
1
1
00
01
10
11
NOTE
Multiplication Factor = RCWL[CEPMF]/
VCO Divider
Reserved
(1 + RCWL[CEPDF])
QUICC Engine PLL
4
8
2
× 10.5
× 11.5
× 12.5
× 13.5
× 14.5
× 5.5
× 6.5
× 7.5
× 8.5
× 9.5
Freescale Semiconductor

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