MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 106

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges
of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
2.22.1
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package
pins, into a test/measurement load shown in the following figure.
2.23
This section describes the PLL configuration of the chip. Note that the platform clock is identical to the core complex bus (CCB)
clock.
106
Clocking
Compliance Test and Measurement Load
Figure 70. Minimum Receiver Eye Timing and Voltage Compliance Specification
The reference impedance for return loss measurements is 50. to ground for both the D+ and
D- line (that is, as measured by a Vector Network Analyzer with 50. probes—see
Figure
measurement.
The allowance of the measurement point to be within 0.2 inches of the package pins is
meant to acknowledge that package/board routing may benefit from D+ and D– not being
exactly matched in length at the package pin boundary.
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
(D+, D– Crossing Point
71). Note that the series capacitors, CTX, are optional for the return loss
V
RX-DIFF
D+ Package
D+ Package
D– Package
= 0 mV
Figure 71. Compliance Test/Measurement Load
+ Package
Silicon
Pin
Pin
Pin
TX
V
RX-DIFFp-p-MIN
0.4 UI = T
C = C
C = C
NOTE
NOTE
R = 50 Ω
RX-EYE-MIN
TX
TX
> 175 mV
(D+, D– Crossing Point
R = 50 Ω
V
RX-DIFF
= 0 mV
Freescale Semiconductor