HW-V5-ML501-UNI-G Xilinx Inc, HW-V5-ML501-UNI-G Datasheet - Page 39

• Manufacturer Part Number: HW-V5-ML501-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr
• Type: FPGAr

Specifications of HW-V5-ML501-UNI-G

• Design Resources: ML501 Ref Design User Guide ML501 Schematics
• Contents: ML501 Platform, DVI Adapter and CompactFlash Card
• Silicon Manufacturer: Xilinx
• Features: Programmable System Clock Generator Chip, RS-232 Serial Port
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50FFG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: XC5VLX50FFG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1508

Programming the IDT Clock Chip
Overview
Downloading to the ML50x Board
ML501 Evaluation Platform
UG226 (v1.4) August 24, 2009
R
ML50x evaluation boards feature an Integrated Device Technology (IDT) 3.3V EEPROM
Programmable Clock Generator that is pre-programmed at the factory. In the event the
chip programming is changed, the instructions in this appendix show how to return the
clock chip to its factory default settings using the following equipment:
•
•
1.
2.
3.
4.
5.
6.
7.
Xilinx download cable
JTAG flying wires
Connect a Xilinx download cable to the board using flying leads connected to jumper
J3
Set a jumper across J14 to enable JTAG programming of the IDT clock chip.
Click Start → iMPACT.
Click Boundary Scan.
Right-click Add Xilinx Device…
Locate the SVF file (ML50X_clock_setup.svf in the example shown in
page
Note:
Right-click on the device and select Execute XSVF/SVF.
(Figure
40) and click Open.
The ML50X_clock_setup.svf file is available on the ML50x product page.
A-1).
Figure A-1: J3 IDT5V9885 JTAG Connector
www.xilinx.com
CLK Prog
1
J3
UG226_apdx_a_01_031207
TMS
TDI
TDO
TCK
GND
3.3V
Appendix A
Figure A-2,
39