EVAL-ADUC7023QSPZ Analog Devices Inc, EVAL-ADUC7023QSPZ Datasheet - Page 10

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EVAL-ADUC7023QSPZ

Manufacturer Part Number
EVAL-ADUC7023QSPZ
Description
KIT DEV FOR ADUC7023 QUICK START
Manufacturer
Analog Devices Inc
Type
MCUr
Datasheet

Specifications of EVAL-ADUC7023QSPZ

Contents
Board
Silicon Manufacturer
Analog Devices
Core Architecture
ARM
Core Sub-architecture
ARM7TDMI
Silicon Core Number
ADuC7023
For Use With/related Products
ARM7TDMI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADuC7023
Table 5. SPI Master Mode Timing (Phase Mode = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
1
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
t
UCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data output setup before SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
SCLK
SCLK
MOSI
MISO
t
DOSU
t
DSU
1
MSB IN
1
t
MSB
DHD
t
SH
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
t
DF
t
DAV
1
1
t
SL
Rev. B | Page 10 of 96
t
DR
BIT 6 TO BIT 1
BIT 6 TO BIT 1
Min
1 × t
2 × t
UCLK
UCLK
LSB IN
t
SR
(SPIDIV + 1) × t
Typ
(SPIDIV + 1) × t
5
5
5
5
LSB
t
SF
UCLK
UCLK
Max
25
75
12.5
12.5
12.5
12.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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