EVAL-ADUC7023QSPZ Analog Devices Inc, EVAL-ADUC7023QSPZ Datasheet - Page 75
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EVAL-ADUC7023QSPZ
Manufacturer Part Number
EVAL-ADUC7023QSPZ
Description
KIT DEV FOR ADUC7023 QUICK START
Manufacturer
Analog Devices Inc
Type
MCUr
Datasheet
1.EVAL-ADUC7023QSPZ.pdf
(96 pages)
Specifications of EVAL-ADUC7023QSPZ
Contents
Board
Silicon Manufacturer
Analog Devices
Core Architecture
ARM
Core Sub-architecture
ARM7TDMI
Silicon Core Number
ADuC7023
For Use With/related Products
ARM7TDMI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 22 interrupt sources on the ADuC7023 that are
controlled by the interrupt controller. Most interrupts are
generated from the on-chip peripherals, such as ADC. Four
additional interrupt sources are generated from external
interrupt request pins, IRQ0, IRQ1, IRQ2, and IRQ3. The
ARM7TDMI CPU core only recognizes interrupts as one of two
types, a normal interrupt request IRQ or a fast interrupt request
FIQ. All the interrupts can be masked separately.
The control and configuration of the interrupt system is
managed through nine interrupt related registers, four
dedicated to IRQ, and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source. The
bits in each IRQ and FIQ registers represent the same interrupt
source as described in Table 87.
The ADuC7023 contains a vectored interrupt controller (VIC)
that supports nested interrupts up to eight levels. The VIC also
allows the programmer to assign priority levels to all interrupt
sources. Interrupt nesting is enabled by setting the ENIRQN bit
in the IRQCONN register. A number of extra MMRs are used
when the full-vectored interrupt controller is enabled.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.
Table 87. IRQ/FIQ MMRs Bit Description
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Description
All interrupts OR’ed (FIQ only).
SWI.
Timer0.
Timer1.
Watchdog timer (Timer 2).
Flash control.
ADC channel.
PLL lock.
I
I
I
I
SPI.
External IRQ0.
Comparator.
PSM.
External IRQ1.
PLA IRQ0.
External IRQ2.
External IRQ3.
PLA IRQ1.
PWM.
2
2
2
2
C0 master.
C0 slave.
C1 master.
C1 slave.
Rev. B | Page 75 of 96
IRQ
The interrupt request (IRQ) is the exception signal to enter the
IRQ mode of the processor. It is used to service general-purpose
interrupt handling of internal and external events.
The four 32-bit registers dedicated to IRQ are: IRQSTA,
IRQSIG, IRQEN, and IRQCLR.
IRQSTA Register
Name:
Address:
Default value:
Access:
Function:
IRQSIG Register
Name:
Address:
Default value:
Access:
Function:
IRQSTA
0xFFFF0000
0x00000000
Read
IRQSTA (read-only register) provides the
current-enabled IRQ source status. When
set to 1, that source generates an active IRQ
request to the ARM7TDMI core. There is no
priority encoder or interrupt vector
generation. This function is implemented in
software in a common interrupt handler
routine. All 32 bits are logically OR’ e d to
create the IRQ signal to the ARM7TDMI
core.
IRQSIG
0xFFFF0004
0x00XXX000
Read
IRQSIG reflects the status of the different IRQ
sources. If a peripheral generates an IRQ
signal, the corresponding bit in the IRQSIG is
set; otherwise, it is cleared. The IRQSIG bits
are cleared when the interrupt in the
particular peripheral is cleared. All IRQ
sources can be masked in the IRQEN MMR.
IRQSIG is read-only.
ADuC7023