EVAL-ADUC7023QSPZ Analog Devices Inc, EVAL-ADUC7023QSPZ Datasheet - Page 72
EVAL-ADUC7023QSPZ
Manufacturer Part Number
EVAL-ADUC7023QSPZ
Description
KIT DEV FOR ADUC7023 QUICK START
Manufacturer
Analog Devices Inc
Type
MCUr
Datasheet
1.EVAL-ADUC7023QSPZ.pdf
(96 pages)
Specifications of EVAL-ADUC7023QSPZ
Contents
Board
Silicon Manufacturer
Analog Devices
Core Architecture
ARM
Core Sub-architecture
ARM7TDMI
Silicon Core Number
ADuC7023
For Use With/related Products
ARM7TDMI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (2Mb)
ADuC7023
On power-up, PWMCON1 defaults to 0x0012 (HOFF = 1 and
HMODE = 1). All GPIO pins associated with the PWM are
configured in PWM mode by default (see Table 85). Clear the
PWM trip interrupt by writing any value to the PWMCLRI
Table 85. PWM Output Selection
ENA
0
X
1
1
1
1
1
2
Table 86. Compare Registers
Name
PWM0COM0
PWM0COM1
PWM0COM2
PWM1COM0
PWM1COM1
PWM1COM2
PWM2COM0
PWM2COM1
HS = high side, LS = low side.
X is don’t care.
HOFF
0
1
0
0
0
0
PWMCON1 MMR
POINV
X
X
0
0
1
1
0xFFFF0F84
0xFFFF0F88
0xFFFF0F8C
0xFFFF0F94
0xFFFF0F98
0xFFFF0F9C
0xFFFF0FA4
0xFFFF0FA8
Address
1
DIR
X
X
0
1
0
1
Rev. B | Page 72 of 96
PWM0
1
1
0
HS1
HS1
1
Default Value
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
MMR. Note that when using the PWM trip interrupt, clear the
PWM interrupt before exiting the ISR. This prevents generation
of multiple interrupts.
PWM1
1
0
0
LS1
LS1
1
PWM Outputs
PWM2
1
1
HS1
0
1
HS1
2
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM3
1
0
LS1
0
1
LS1
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