C8051F360-TB Silicon Laboratories Inc, C8051F360-TB Datasheet - Page 188

BOARD TARGET/PROTO W/C8051F360

C8051F360-TB

Manufacturer Part Number
C8051F360-TB
Description
BOARD TARGET/PROTO W/C8051F360
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F360-TB

Contents
Board
Processor To Be Evaluated
C8051F36x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F360
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1412
C8051F360/1/2/3/4/5/6/7/8/9
188
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
SFR Page:
SFR Address:
CP1AE
R/W
Bit7
CP1AE: Comparator1 Asynchronous Output Enable
0: Asynchronous CP1 unavailable at Port pin.
1: Asynchronous CP1 routed to Port pin.
CP1E: Comparator1 Output Enable
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
CP0AE: Comparator0 Asynchronous Output Enable
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
CP0E: Comparator0 Output Enable
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SYSCKE: /SYSCLK Output Enable
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK (divided by 1, 2, 4, or 8) routed to Port pin. The divide factor is determined by
the CLKDIV1–0 bits in register CLKSEL (See Section Section “16. Oscillators” on
page 169).
SMB0E: SMBus I/O Enable
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
SPI0E: SPI I/O Enable
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins.
URT0E: UART I/O Output Enable
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.1 and P0.2 (C8051F360/3) or P0.4 and P0.5
F
0xE1
(C8051F361/2/4/5/6/7/8/9).
CP1E
SFR Definition 17.1. XBR0: Port I/O Crossbar Register 0
R/W
Bit6
CP0AE
R/W
Bit5
CP0E
R/W
Bit4
SYSCKE
Rev. 1.0
R/W
Bit3
SMB0E
R/W
Bit2
SPI0E
R/W
Bit1
URT0E
R/W
Bit0
00000000
Reset Value

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