C8051F360-TB Silicon Laboratories Inc, C8051F360-TB Datasheet - Page 194

• Manufacturer Part Number: C8051F360-TB
• Description: BOARD TARGET/PROTO W/C8051F360
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360-TB

• Contents: Board
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1412

C8051F360/1/2/3/4/5/6/7/8/9
194
Bits 7–0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in regis-
Bits 7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits.
Bits 7–0: P1MAT[7:0]: Port1 Match Value.
SFR Page:
SFR Address:
SFR Page:
SFR Address:
SFR Page:
SFR Address:
R/W
R/W
R/W
Bit7
Bit7
Bit7
ter P1MDIN is logic ‘0’.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (V
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
These bits control the value that unmasked P0 Port pins are compared against. A Port
Match event is generated if (P1 & P1MASK) does not equal (P1MAT & P1MASK).
F
0xA5
F
0xD5
0
0xE1
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 17.11. P1MDOUT: Port1 Output Mode
SFR Definition 17.13. P1MAT: Port1 Match
SFR Definition 17.12. P1SKIP: Port1 Skip
R/W
R/W
R/W
Bit5
Bit5
Bit5
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.0
R/W
R/W
R/W
Bit3
Bit3
Bit3
R/W
R/W
R/W
Bit2
Bit2
Bit2
R/W
R/W
R/W
Bit1
Bit1
Bit1
REF
input, external oscil-
R/W
R/W
R/W
Bit0
Bit0
Bit0
00000000
Reset Value
Reset Value
00000000
Reset Value
11111111