C8051F360-TB Silicon Laboratories Inc, C8051F360-TB Datasheet - Page 203
![BOARD TARGET/PROTO W/C8051F360](/photos/9/25/92554/c8051f360-tb_sml.jpg)
C8051F360-TB
Manufacturer Part Number
C8051F360-TB
Description
BOARD TARGET/PROTO W/C8051F360
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F360-TB
Contents
Board
Processor To Be Evaluated
C8051F36x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F360
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1412
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18.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
18.2. SMBus Configuration
Figure 18.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-direc-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
18.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is
received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see
Figure 18.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
1. The I
2. The I
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
V
DD
= 5 V
2
2
C-Bus and How to Use It (including specifications), Philips Semiconductor.
C-Bus Specification—Version 2.0, Philips Semiconductor.
Figure 18.2. Typical SMBus Configuration
V
Master
Device
DD
= 3 V
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
Device 1
V
DD
Slave
= 5 V
Device 2
V
DD
Slave
= 3 V
SDA
SCL
203
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