C8051F360-TB Silicon Laboratories Inc, C8051F360-TB Datasheet - Page 243

• Manufacturer Part Number: C8051F360-TB
• Description: BOARD TARGET/PROTO W/C8051F360
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360-TB

• Contents: Board
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1412

Bits 7–0: SCR7–SCR0: SPI0 Clock Rate.
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
SFR Page:
SFR Address:
f
Bits 7–0: SPI0DAT: SPI0 Transmit and Receive Data.
SFR Page:
SFR Address:
SCK
SCR7
f
SCK
R/W
Bit7
R/W
Bit7
=
=
These bits determine the frequency of the SCK output when the SPI0 module is configured
for master mode operation. The SCK clock frequency is a divided version of the system
clock, and is given in the following equation, where SYSCLK is the system clock frequency
and SPI0CKR is the 8-bit value held in the SPI0CKR register.
for 0 <= SPI0CKR <= 255
f
200kHz
SCK
all pages
0xA2
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT
places the data into the transmit buffer and initiates a transfer when in Master Mode. A read
of SPI0DAT returns the contents of the receive buffer.
------------------------- -
2
all pages
0xA3
2000000
SCR6
×
R/W
Bit6
(
=
R/W
Bit6
4
+
------------------------------------------------ -
2
×
1
SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate
)
(
SPI0CKR
SCR5
SYSCLK
R/W
Bit5
SFR Definition 20.4. SPI0DAT: SPI0 Data
R/W
Bit5
SCR4
+
R/W
Bit4
1
R/W
Bit4
)
C8051F360/1/2/3/4/5/6/7/8/9
SCR3
Rev. 1.0
R/W
Bit3
R/W
Bit3
SCR2
R/W
Bit2
R/W
Bit2
SCR1
R/W
Bit1
R/W
Bit1
SCR0
R/W
Bit0
R/W
Bit0
00000000
Reset Value
00000000
Reset Value
243