C8051F040-TB Silicon Laboratories Inc, C8051F040-TB Datasheet - Page 218

• Manufacturer Part Number: C8051F040-TB
• Description: BOARD PROTOTYPING W/C8051F040
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F040-TB

• Contents: Board
• Processor To Be Evaluated: C8051F04x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F040
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F040/1/2/3/4/5/6/7
218
Bits7-0:
Note:
Bits7-0:
P2.7
R/W
R/W
Bit7
Bit7
P2.[7:0]: Port2 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P2MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P2.n pin is logic low.
1: P2.n pin is logic high.
P2.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multi-
plexed mode, or as Address[7:0] in Non-multiplexed mode). See
Data Memory Interface and On-Chip XRAM” on page 187
External Memory Interface.
P1MDIN.[7:0]: Port 2 Input Mode Bits.
0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from
the Port bit will always return ‘0’). The weak pullup on the pin is disabled.
1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic
level at the Pin. The state of the weak pullup is determined by the WEAKPUD bit (XBR2.7,
see SFR Definition 17.3).
P2.6
R/W
R/W
Bit6
Bit6
SFR Definition 17.11. P2MDIN: Port2 Input Mode
P2.5
R/W
R/W
Bit5
Bit5
SFR Definition 17.10. P2: Port2 Data
P2.4
R/W
R/W
Bit4
Bit4
Rev. 1.5
P2.3
R/W
R/W
Bit3
Bit3
P2.2
R/W
R/W
Bit2
Bit2
P2.1
for more information about the
R/W
R/W
Bit1
Bit1
Section “16. External
SFR Address:
SFR Address:
SFR Page:
SFR Page:
P2.0
R/W
R/W
Bit0
Bit0
0xAE
F
0xA0
All Pages
Reset Value
Reset Value
Addessable
11111111
11111111
Bit