C8051F040-TB Silicon Laboratories Inc, C8051F040-TB Datasheet - Page 223
C8051F040-TB
Manufacturer Part Number
C8051F040-TB
Description
BOARD PROTOTYPING W/C8051F040
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F040-TB
Contents
Board
Processor To Be Evaluated
C8051F04x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F040
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Bits7-0:
Note:
Bits7-0:
P5.7
R/W
R/W
Bit7
Bit7
P5.[7:0]: Port5 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P5MDOUT bit = 0). See SFR Definition
17.19.
Read - Returns states of I/O pins.
0: P5.n pin is logic low.
1: P5.n pin is logic high.
P5.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-mul-
tiplexed mode). See
on page 187
P5MDOUT.[7:0]: Port5 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
P5.6
R/W
R/W
Bit6
Bit6
SFR Definition 17.19. P5MDOUT: Port5 Output Mode
for more information about the External Memory Interface.
P5.5
R/W
R/W
Bit5
Bit5
SFR Definition 17.18. P5: Port5 Data
Section “16. External Data Memory Interface and On-Chip XRAM”
P5.4
R/W
R/W
Bit4
Bit4
Rev. 1.5
P5.3
R/W
R/W
Bit3
Bit3
C8051F040/1/2/3/4/5/6/7
P5.2
R/W
R/W
Bit2
Bit2
P5.1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
P5.0
R/W
R/W
Bit0
Bit0
0xD8
F
0x9D
F
Addressable
00000000
Reset Value
Reset Value
11111111
Bit
223
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