MPC8308-RDB Freescale Semiconductor, MPC8308-RDB Datasheet - Page 28

• Manufacturer Part Number: MPC8308-RDB
• Description: BOARD REF DESIGN MPC8308
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8308-RDB

• Contents: Board, Cables, Documentation, Power Supply, Software
• Ethernet Connection Type: Serial to Ethernet
• Data Rate: 10 Mbps, 100 Mbps, 1000 Mbps
• Memory Type: DDR2, SDRAM
• Interface Type: HSSI
• Operating Voltage: 1.5 V
• Operating Current: 5 uA
• Maximum Power Dissipation: 1000 mW
• Operating Temperature Range: - 55 C to + 125 C
• Product: Modules
• For Use With/related Products: MPC8308
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Speed Serial Interfaces (HSSI)
10.2.2
The DC level requirement for the MPC8308 SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
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Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV
— For external DC-coupled connection, as described in
— For external AC-coupled connection, there is no common mode voltage requirement for the
Single-ended Mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude
— The SD_REF_CLK input average voltage must be between 200 and 400 mV.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
differential peak-peak (or between 200 mV and 800 mV differential peak). In other words,
each signal wire of the differential pair must have a single-ended swing less than 800 mV and
greater than 200 mV. This requirement is the same for both external DC-coupled or
AC-coupled connection.
Clock Receiver Characteristics,”
requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV.
Figure 17
scheme.
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
XCOREVSS. Each signal wire of the differential inputs is allowed to swing below and above
the common mode voltage (XCOREVSS).
requirement for AC-coupled connection scheme.
(single-ended swing) must be between 400 mV and 800 mV peak-peak (from Vmin to Vmax)
with SD_REF_CLK either left unconnected or tied to ground.
the SerDes reference clock input requirement for single-ended signaling mode.
AC-coupled externally. For the best noise performance, the reference of the clock could be DC
or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as
the clock input (SD_REF_CLK) in use.
DC Level Requirement for SerDes Reference Clocks
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2
shows the SerDes reference clock input requirement for DC-coupled connection
the maximum average current requirements sets the
Figure 18
shows the SerDes reference clock input
Section 10.2.1, “SerDes Reference
Freescale Semiconductor
Figure 19
shows