MPC8308-RDB Freescale Semiconductor, MPC8308-RDB Datasheet - Page 51

• Manufacturer Part Number: MPC8308-RDB
• Description: BOARD REF DESIGN MPC8308
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8308-RDB

• Contents: Board, Cables, Documentation, Power Supply, Software
• Ethernet Connection Type: Serial to Ethernet
• Data Rate: 10 Mbps, 100 Mbps, 1000 Mbps
• Memory Type: DDR2, SDRAM
• Interface Type: HSSI
• Operating Voltage: 1.5 V
• Operating Current: 5 uA
• Maximum Power Dissipation: 1000 mW
• Operating Temperature Range: - 55 C to + 125 C
• Product: Modules
• For Use With/related Products: MPC8308
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2.2
Figure 36
13.3
Table 40
At recommended operating conditions NV
Freescale Semiconductor
SD_CLK clock frequency—high speed mode
SD_CLK clock cycle
SD_CLK clock frequency—identification mode
SD_CLK clock low time
SD_CLK clock high time
SD_CLK clock rise and fall times
Input setup times: SD_CMD, SD_DATx
Input hold times: SD_CMD, SD_DATx
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid
SD Card Input Setup
SD Card Input Hold
provides the eSDHC AC timing specifications.
eSDHC AC Timing Specifications
provides the data and command input timing diagram.
Full Speed Input Path (Read)
Output from the
MPC8308 Pins
SD CLK at the
MPC8308 Pin
SD Card Pins
the Card Pin
Input at the
SD CLK at
Table 40. eSDHC AC Timing Specifications for High Speed Mode
Parameter
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2
DD
= 3.3 V ± 300 mV.
Figure 36. Full Speed Input Path
Driving
Symbol
t
t
t
t
t
t
SHSKHOV
t
t
SHSKHOX
Edge
SHSCKR/
SHSIVKH
SHSIXKH
SHSCKH
f
t
SHSCKL
SHSCKF
t
f
SHSCK
SHSCK
ODLY
SIDCK
t
t
t
ISU
OH
IH
t
t
SFSIXKH
SFSCK
1
t
CLK_DELAY
(Clock Cycle)
Enhanced Secure Digital Host Controller (eSDHC)
Min
20
–3
—
t
0
0
7
7
3
2
3
6
2
SFSIVKH
t
DATA_DELAY
Max
400
50
—
—
—
—
—
—
—
—
—
3
(MPC8308 Input Hold)
Sampling
Edge
MHz
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
—
—
3
2
2
2
2
2
2
2
3
3
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