MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 62

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI
15.2
This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is
used as the PCI input clock.
Figure 41
62
SYSCLK to output valid
Output hold from SYSCLK
SYSCLK to output high impedance
Input setup to SYSCLK
Input hold from SYSCLK
REQ64 to HRESET
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
Rise time (20%–80%)
Fall time (20%–80%)
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. All PCI signals are measured from OV
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
5. Input timings are measured at the pin.
6. The timing parameter t
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter t
9. The reset assertion timing requirement for HRESET is 100 μs.
inputs and t
(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, t
going to the high (H) state or setup time. Also, t
went high (H) relative to the frame signal (F) going to the valid (V) state.
3.3-V PCI signaling levels.
through the component pin is less than or equal to the leakage current specification.
system clock period must be kept within the minimum and maximum defined ranges. For values see
Specifications.
PCI AC Electrical Specifications
provides the AC test load for PCI.
(first two letters of functional block)(reference)(state)(signal)(state)
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
9
setup time
Parameter
SYS
PCRHFV
Output
indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
Table 56. PCI AC Timing Specifications at 66 MHz
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
Table 56
DD
/2 of the rising edge of PCI_SYNC_IN to 0.4 × OV
provides the PCI AC timing specifications at 66 MHz.
Figure 41. PCI AC Test Load
Z
PCRHFV
0
= 1 KΩ
symbolizes PCI timing (PC) with respect to the time hard reset (R)
Symbol
t
t
t
t
t
t
t
t
t
t
PCKHOV
PCKHOX
PCKHOZ
PCRVRH
PCRHRX
PCRHFV
PCIVKH
PCIXKH
PCICLK
PCICLK
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
1
R
L
10 × t
= 50 Ω
Min
2.0
3.7
0.5
0.6
0.6
10
—
—
0
SYS
OV
DD
DD
PCIVKH
Max
7.4
2.1
2.1
/2
14
50
—
—
—
—
—
of the signal in question for
Freescale Semiconductor
symbolizes PCI timing
Section 19, “Clocking.”
SYS
clocks
clocks
Unit
ns
ns
ns
ns
ns
ns
ns
ns
, reference (K)
Notes
2, 3
2, 4
2, 5
2, 5
6, 7
—
—
for
2
7
8